AK8850 Datasheet, PDF (67/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
7-4-22 POWER SAVE MODE
The AK8850 is placed in Power Save mode by setting the PS-bit of the [ POWER SAVE MODE REGISTER ] to “ 1 “.
Exiting Power Save mode is done by setting the PS-bit to “0”. During Power Save mode, the I2C bus controller, clock
output driver and VREF generating circuit are active, the PLL block is initialized and PLL DAC local code becomes 0x80.
After exiting Power Save mode, the device re-starts operation from the state which is set via the I2C bus.
All circuits are put into Sleep mode when the Power Down pin ( PD ) is set to high.
The IVCXO output current is zero micro Amps in this state. To re-start the AK8850, an input reset and initialization are
required after setting PD pin from high to low. Operation is stabilized in a few milliseconds.
Please follow the Power Down set sequence for proper setting.
Power Save Mode Related Register :
Power Save related registers are programmed by the [ POWER SAVE MODE REGISTER ].
* [ POWER SAVE MODE REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved Reserved Reserved PLLRST
ADC3
ADC2
ADC1
PS
Default Value
0
0
0
0
0
0
0
0
* PS-bit set
PS-bit
0
1
Function
Normal function
Stops the clock supply to the Internal digital Block, exclusive
control block..
Stops ADC1/2/3. Resets the PLL control circuit.
Note
* ADC1 / 2 / 3-bit set
ADC1/2/3-bit
0
1
Function
ADC1/2/3 Active mode
ADC1/2/3 sleep mode
Note
Each ADC can be set to sleep mode individually.
Rev.0
67
2003/01