AK8850 Datasheet, PDF (73/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
OUTPUT CONTROL REGISTER ( R / W ) [ SUB ADDRESS 0x05 ]
Thie register sets the external output signal attributes like HSYNC, VSYNC, FIELD, DVALID and FRAME etc. Timing of
output signals can be altered by CLKOUT-bit set.
Sub Address 0x05
bit 7
bit 6
VDVSYNC FFDELAY
bit 5
HALFCLK
0
0
0
bit 4
bit 3
FRAME
DVALVLK
Default Value
1
0
bit 2
FIELD
1
Default Value : 0x14
bit 1
bit 0
VSYNC
HSYNC
0
0
Output Control Register Definition
BIT Register Name
bit 0
HSYNC
HSYNC-Logic bit
bit 1
VSYNC
VSYNC-Logic bit
bit 2
FIELD
FIELD-Logic bit
bit 3 DVAL/VLK DVALID VLock Switch- bit
bit 4
FRAME
FRAME-Logic bit
bit 5 HALFCLK HALFCLK-bit
bit 6 FFDELAY Field Frame Delay bit
bit 7 VDVSYNC VD/VSYNC Select bit
R/W Definition
0 : Low [default]
R/W 1 : High
0 : Low[default]
R/W 1 : High
0 : ODD FIELD : Low
R/W 1 : ODD FIELD : High [default]
0 : DVALID signal output [default]
R/W 1 : VLOCK status output
0 : Low at CF = 0
R/W 1 : High at CF = 0[default]
0 : Low at Y-data ouput timing [ Default]
R/W 1 : Hight at Y-data output
Field timing signal and Frame timing signal can
R/W be output 0.5H delayed with this bit.
0 : No Delay [default]
1 : 0.5H Delay
0 : Output VSYNC Pulse [default]
R/W 1 : Ouput VD pulse.
(Refer to the Figure “Output timing Signal”)
FIELD and FRAME signals are correct values only when the Standard signal is input. ( in case of Non-Standard signal
input, FIELD and FRAME signals are not necessarily correct ones .For handling of Non-Standard signal input,refer to item
7-4-21 ).
Rev.0
73
2003/01