AK8850 Datasheet, PDF (80/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
PGA1 Gain Control Register (R/W) [Sub Address 0x0D]
Sub Address 0x0D
bit 7
bit 6
bit 5
bit 4
bit 3
Reserved PGA1[6]
PGA1[5]
PGA1[4]
PGA1[3]
Default Value
0
1
0
0
0
bit 2
PGA1[2]
0
Default Value : 0x40
bit 1
bit 0
PGA1[1]
PGA1[0]
0
0
PGA1 Gain Control Register
BIT Register Name
bit 0
PGA1[0]
bit 6
PGA1[6]
bit 7 Reserved
PGA1[0]
PGA1[6] bit
Reserved
R/W Definition
Setting PGA1 Gain.
R/W This register is available when Control 1
Register is set to [bit-1,0] = [0,0] (AGC Disable)
Gain step of PGA is about 0.1dB/LSB.
R/W Reserved
PGA2 Gain Control Register (R/W) [Sub Address 0x0E]
Sub Address 0x0E
bit 7
bit 6
bit 5
bit 4
bit 3
Reserved PGA2[6]
PGA2[5]
PGA2[4]
PGA2[3]
Default Value
0
1
0
0
0
bit 2
PGA2[2]
0
Default Value : 0x40
bit 1
bit 0
PGA2[1]
PGA2[0]
0
0
PGA2 Gain Control Register
BIT Register Name
bit 0
PGA2[0]
bit 6
PGA2[6]
bit 7 Reserved
PGA2[0]
PGA2[6] bit
Reserved
R/W Definition
Setting PGA2 Gain.
R/W This register is available when Control 1
Register is set to [bit-1,0] = [0,0] (AGC Disable)
Gain step of PGA is about 0.1dB/LSB.
R/W Reserved
PGA3 Gain Control Register (R/W) [Sub Address 0x0F]
Sub Address 0x0F
bit 7
bit 6
bit 5
bit 4
bit 3
Reserved PGA3[6]
PGA3[5]
PGA3[4]
PGA3[3]
Default Value
0
1
0
0
0
bit 2
PGA3[2]
0
Default Value : 0x40
bit 1
bit 0
PGA3[1]
PGA3[0]
0
0
PGA3 Gain Control Register
BIT Register Name
bit 0
PGA3[0]
bit 6
PGA3[6]
bit 7 Reserved
PGA3[0]
PGA3[6] bit
Reserved
R/W Definition
Setting PGA3 Gain.
R/W This register is available when Control 1
Register is set to [bit-1,0] = [0,0] (AGC Disable)
Gain step of PGA is about 0.1dB/LSB.
R/W Reserved
Rev.0
80
2003/01