AK8850 Datasheet, PDF (19/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
5-3. Output Signal Timing Diagram ( CCIR625 Component input )
The VERTICAL Sync signal, FIELD signal and FRAME signal timing relationships are shown. The logical state of HSYNC/VSYNC/FIELD/FRAME can be altered by using register settings.
Either VSYNC or VD output signals are available on the VSYNC output pin, depending upon the register setting. The FIELD output and the FRAME output signals change state on the
rising edge of the CSYNC, prior to the 0.5H delay period that is controlled by the output control register. Field/FRAME output timings are shown on pages 20 and 21.
CSYNC
62
62
62
62
62
62
1
2
3
4
5
6
7
8
HSYNC
VSYNC
VD
FIELD
EVEN
ODD
FRAME
CSYNC
HSYNC
30
30
31
31
31
31
31
31
31
31
31
VSYNC
VD
FIELD
ODD
FRAME ^(Low)
EVEN
31
32
32
CSYNC
62
62
HSYNC
VSYNC
VD
FIELD
FRAME
62
62
EVEN
62
62
1
2
3
ODD
4
5
6
7
8
CSYNC
HSYNC
30
30
VSYNC
VD
FIELD
FRAME
(High
31
31
31
31
31
31
31
31
31
ODD
EVEN
31
32
32
Rev.0
19
2002/0