AK8850 Datasheet, PDF (92/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
CLOCK CONTROL-1 REGISTER ( R /W ) [ SUB ADDRESS 0x36 ]
This register controls the Clock transition time in Auto Clock mode which is set by [ bit 7 : bit 6 ] of the Auto Select
( CONTROL 2 REGISTER ( 0x09 ))
Sub Address 0x36
bit 7
bit 6
TTC1
TTC0
1
0
bit 5
SKEWTH5
0
bit 4
bit 3
SKEWTH4 SKEWTH3
Default Value
0
0
bit 2
SKEWTH2
1
Default Value : 0x84
bit 1
bit 0
SKEWTH1 SKEWTH0
0
0
Clock Control-1 Register Definition
BIT Register Name
bit 0 SKEWTH0 Skew Detection Threshold
~
bit 5 SKEWTH5
bit 6
TTC0
Clock Transition Time Constant
bit 7
TTC1
R/W Definition
R/W Set the threshold value for VTR Skew detection.
Threshold value = [SKEWTH5:SKEWTH0]
Time Constant for clock mode transition.
0 : slowest
3 : fastest
CLOCK CONTROL-2 REGISTER ( R / W ) [ SUB ADDRESS 0x37 ]
This register controls the Clock Transition time in Auto Clock mode which is set by [ bit 7 : bit 6 ] of the Auto Select Control
2 Register ( 0x09 ).
Sub Address 0x37
bit 7
bit 6
LNFRTH7 LNFRTH6
0
1
bit 5
LNFRTH5
1
bit 4
bit 3
LNFRTH4 LNFRTH3
Default Value
1
1
bit 2
LNFRTH2
1
Default Value : 0x7C
bit 1
bit 0
LNFRTH1 LNFRTH0
0
0
Clock Control-2 Register Definition
BIT Register Name
R/W Definition
bit 0 LNFRTH0 Lint to Frame Threshold Level R/W The threshold parameter from Line-Lock clock
~
Control bit
mode to Frame-Lock clock mode.
bit 7 LNFRTH7
Rev.0
92
2003/01