AK8850 Datasheet, PDF (53/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
VBIDEC-bit is the control bit that specifies the device operation during the period is assigned by VBI [4 : 0]-bit. The output
code is determined by the VBI period , VBIDEC-bit, HALFSU-bit and SETUP-bit of the [ INPUT VIDEO STANDARD
REGISTER ]. When HALFSU-bit = 1, the SETUP processing is executed on the latter half 0.5 H time of the first Line in the
second Field.
Output status is shown in the following table.
NTSC (525 System)
Line-1
-
Line-9
Line-10
-
[VBIL4:VBIL0]
[VBIL4:VBIL0] + 1
-
Line-263.5
(till 429th pixel of Line-263)
Line-263.5
(from 430th pixel of Line-263)
-
Last pixel of Line263
Line-264
-
Line-272.5
(till 429th pixel of Line272)
Line-272.5
(from 430th pixel of Line-272)
-
263.5 + [VBIL4:VBIL0]
(till 429th pixel of
Line(263+[VBIL4:VBIL0]))
263.5 + [VBIL4:VBIL0]
(from 430th pixel of
Line(263+[VBIL4:VBIL0]))
-
Line-263.5 + Last pixel of
[VBIL4:VBIL0]
(858th pixel of Line(263+[VBIL4:VBIL0]))
Line-264 + [VBIL4:VBIL0]
-
Line-525
Line-1
-
Line-9
Line-10
-
[VBIL4:VBIL0]
[VBIL4:VBIL0] + 1
-
Line-263.5
Line-263 429
Line-263.5
(from 430th pixel of Line-263)
-
the last pixel of Line263
Line-264
-
Line-272.5
(till 429th pixel of Line272)
Line-272.5
(from 430th pixel of Line-272)
-
263.5 + [VBIL4:VBIL0]
(till 429th pixel of
Line(263+[VBIL4:VBIL0]))
263.5 + [VBIL4:VBIL0]
(from 430th pixel of
Line(263+[VBIL4:VBIL0]))
-
the last pixel of Line-263.5 +
[VBIL4:VBIL0]
(till 858th pixel of
Line(263+[VBIL4:VBIL0]))
Line-264 + [VBIL4:VBIL0]
-
Line-525
VBIDEC-bit = 0
HALFSU-bit = 0
HALFSU-bit=1
Y = 0x10
C = 0x80
←
Y = 0x10
C = 0x80
←
Normal
decode
procidure
←
No Setup Process
Y = 0x10
C = 0x80
←
Y = 0x10
C = 0x80
←
Y = 0x10
C = 0x80
←
Normal
decode
procidure
←
No Setup Process
Normal
decode
procidure
←
No Setup Process
Y = 0x10
C = 0x80
←
Y = 0x10
C = 0x80
←
Normal
decode
procidure
Setup Process
←
Y = 0x10
C = 0x80
←
Y = 0x10
C = 0x80
←
Y = 0x10
C = 0x80
←
Normal
decode Normal
decode
process
process
No Setup Procedure Setup Process
Normal
decode
process.
Setup Process
←
VBIDEC-bit = 1
HALFSU-bit=0
HALFSU-bit=1
←
←
Y =Input Signal
C = 0x80
←
No Setup Process
←
←
←
←
←
←
Y =Input signal
C = 0x80
←
No Setup Process
←
←
←
←
←
←
Y =Input Signal
C = 0x80
←
No Setup Process
←
←
←
←
←
←
Y =Input Signal
C = 0x80
←
No Setup Process
Normal
decode Normal
decode
process
process.
No Setup process
Setup Process
←
←
Rev.0
53
2003/01