AK8850 Datasheet, PDF (63/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
7-4-19 TIMING OUTPUT
The AK8850 outputs the signals listed below. Output logical states can be altered by the [ OUTPUT CONTROL
REGISTER ]. The state shown is the default value (refer to the Output Timing Diagram ).
Either the VSYNC or VD signals can be output on the VSYNC output pin per the register setting. Output timing of the Field
signal and the Frame signal can be delayed by 0.5 H time using the FFDELAY-bit of the [ OUTPUT CONTROL
REGISTER ]. CSYNC signals can be output via the FRAME1 pin by setting the FRCSYNC-bit of the [ CONTROL 1
REGISTER ] bit-7.
FFDELAY-bit
0
1
Function
FIELD/FRAME timing signal changes at the falling edge of HSYNC of proper line.
FIELD/FRAME timing signal chages at the raising edge of serration pulse of proper line.
FRCSYNC-bit
0
1
Function
Frame timing signal is output from FRAME1pin
CSYNC timing signal is output from FRAME1pin
At 525-Line-System input ( output state at default value )
HSYNC : “ low “ level signal of 4.7 microsec. Duration in 15.734 KHz interval
VSYNC : “ low “ output signal during Line 4 ~ Line 6 / Line 266.5 ~ Line 269.5
( Line 266.5 means from the latter 0.5 H time of Line 266,and Line 269.5 means up to the former 0.5 H time of Line 269 ).
VD : “ low “ output signal during Line1 ~ Line 9 / Line263.5 ~ Line 272.5
( Line 263.5 means from the latter 0.5 H time of Line 263, and Line 272.5 means up to the former 0.5 H time of Line 272 ).
FIELD : Output signal to become “ low “ at Odd Fields, and “ high “ at Even Fields.
FRAME : Color Frame
For non-Standard signal inputs, Field signal toggles at the rate of ( Line numbers per each Frame / 2 ).
Frame signal changes at the rate of Line numbers per each Frame ( Frame signal changes state at Line 4 ).
CSYNC : Composite Sync signal.CSYNC output does not change state.
At 625-Line-System input ( output state at default value )
HSYNC : “ low “ level signal of 4.7 microsec. duration in 15.734 KHz interval
VSYNC : “ low “ output signal during Line 1 ~ Line 3.5 / Line 313.5 ~ Line 315
( Line 3.5 means up to the former 0.5 H time of Line 3,and Line 313.5 means from the latter 0.5 time of Line 313 ).
VD : “ low “ output signal during Line 623.5 ~ Line 5 / Line 311 ~ Line 318.5.
( Line 632.5 means from the the latter 0.5 H time of Line 623, and Line 318.5 means up to the former 0.5 H time of Line
318 ).
FIELD : Output signal to become “ low “ on Odd Fields, and “ high “ on Even Fields.
FRAME : Color Frame
For non-Standard signal inputs, Field signal toggles at the rate of ( Line numbers per each FRAME / 2 ).
Frame signal changes state at the rate of Line numbers per each Frame ( Frame signal changes state at Line 1 ).
CSYNC : Composite Sync signal. CSYNC output does not change state
Data at both rising edge and falling edge of the FIELD signal is Cb data. The FIELD signal and data relationship of
Standard signal inputs is as follows.
FIELD
D[7:0]
Cb Y Cr Y Cb
122T
Cb0 Y0 Cr0 Y1
Rev.0
63
2003/01