AK8850 Datasheet, PDF (35/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
( 1-6-4 ) SETTING OF PEDESTAL CLAMP TIMING PULSE
Both the start position and pulse width of the Pedestal clamp timing pulse are programmable.It is done using the
[ CLAMP TIMING 2 CONTROL REGISTER ].
This is valid only when [ INCLPTMG : FBCLPTMG1 : FBCLPTMG0 ]-bit is set, causing the internal clamp pulse to be
used for Pedestal clamping ( it is invalid if an external clamp pulse is used ).
To monitor the clamp timing pulse generated by an internal clamp timing circuit, proper setting of the [ EXTMON1 :
EXTMON0 ]-bits of the [ CLAMP TIMING1 CONTROL REGISTER ] is required.
* [ CLAMP TIMING2 CONTROL REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SLCLV1
SLCLV0
PCLPWIDTH2 PCLPWIDTH1 PCLPWIDTH0 PSCLPSTAT2 PCLPSTAT1 PCLPSTAT0
Default Value
0
0
0
1
1
1
0
0
The Start position of the Pedestal clamp timing pulse is set by [ PCLPSTA2 : PCLPSTAT0 ]-bit,and the clamp pulse
width is adjusted by [ PCLPWIDTH3 : PCLPWIDTH0 ]-bit.
* When [ PCLPSTA2 : PCLPSTAT0 ]-bit and [ PCLPWIDTH3 : PCLPWIDTH0 ]-bit are valid,the setting is as follows.
[INCLPTMG: FBCLPTMG1:FBCLPTMG0]-bit
Monitoring with EXTCLP
[010]
Available
Internal pedestal clamp timing pulse
[110]
Unavailable
External Pedestal clamp timing pulse
Set the start position and the pulse width of the Pedestal clamp timing pulse.
* Pedestal clamp timing pulse start position set by [ PCLPSTAT2 : PCLPSTAT0 ]-bit
[PCLPSTAT2:PCLPSTAT0]-bit
(bit-2:bit-0)
Start position from the falling edge of
Synchronization pulse
Color subcarrier Cycles from the falling edge of
HSYNC
000
Passed after 118-Clocks (4.37usec)
17Cycles
001
Passed after 126-Clocks (4.65usec)
18Cycles
19Cycles
010
Passed after 132-Clocks (4.88usec)
(Color burst start position of the standard NTSC
video signal)
011
Passed after 140-Clocks (5.18usec)
20Cycles
100
Passed after 148-Clocks (5.49usec)
21Cycles (Default)
101
Passed after 156-Clocks (5.77usec)
22Cycles
110
Passed after 164 Clocks (6.07usec)
23Cycles
111
Passed after 172 Clocks (6.36usec)
24Cycles
[ PCLPSTAT2 : PCLPSTAT0 ]-bit is used to fine-tune the start position which is set to be 2 clocks later [100 ] as default
value.
Clamp pulse start position changes as follows by [ PCLPSTAT2 : PCLPSTAT0 ]-bit.
* Pedestal Clamp pulse width set by [ PCLPWIDTH2 : PCLPWIDTH0]-bit
[PCLPWIDTH2: PCLPWIDTH0]-bit
(bit-6:bit-4)
Pulse width
000
16-Clocks (592nsec)
001
24-Clocks (888nsec)
010
28-Clocks (1.04usec)
011
32-Clocks (1.18usec)
100
40-Clocks (1.48usec)
101
44-Clocks (1.63usec)
110
48-Clocks (1.78usec)
111
52-Clocks (1.92usec)
Pedestal clamp pulse width is set to its default value of [011] via the [ PCLPWIDTH2 : PCLPWIDTH0 ]-bits =( 32 clocks
= 1.18 micro sec ).
The clamp pulse width is adjusted using the [ PCLPWIDTH3 : PCLPWIDTH0 ]-bit as follows.
Rev.0
35
2002/01