AK8850 Datasheet, PDF (52/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
7-4-10 VERTICAL BLANKING INTERVAL
This section describes setting the Vertical Blanking Interval (VBI ) and to set tasks to be performed during this interval.
The Vertical Blanking Interval is set by [ VBIL4 : VBIL0 ]-bit of the [ VERTICAL BLANKING LENGTH
REGISTER ].( hereafter,VBI period means an interval defined by [ VBIL4 : VBIL0 ]-bit ).
Default value is 0x14 ( 20 lines ). For normal operation, it is recommended to set the VBI interval to be more than 9 / 7
( 525 line system / 625 line system ).
The V-bit transition point of the Video Timing Reference Code can be altered by the TRSVSEL-bit of the [ VERTICAL
BLANKING LENGTH REGISTER ]. TRSVSEL-bit selects either of the ITU-R BT.656 or SMPTE 125M Standards
compatibility. The relationship between TRSVSEL-bit and the Video Timing Reference Code V-bit is shown in the table
below.
TRSVSEL-bit
0
1
Standard
ITU-R BT.656
SMPTE125M
During the VBI period, the black level ( Y = 0x10,Cb/Cr= 0x80 ) is output by default.
By setting the VBIDEC-bit of the [ VERTICAL BLANKING LENGTH REGISTER ] to [1], the Y/C Separation function on
those lines which are specified during VBI interval is turned off and input signal is directly output as a Y signal. The
SETUP-bit of the [ INPUT VIDEO STANDARD REGISTER ] becomes invalid during VBI period ( no setup process is
executed ).
Turning the setup process on /off on the latter half of a scan line line ( 0.5 H ) can be controlled by the HALFSU-bit which
is applied only to the first line of the second Field of Active Video.
VBID Control Register Description :
* [ VERTICAL BLANKING LENGTH REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
VBIDEC TRSVSEL HALFSU
VBIL4
VBIL3
Default Value
0
0
0
1
0
bit 2
VBIL2
1
bit 1
VBIL1
0
bit 0
VBIL0
0
The VBI period is set by [ VBIL4 : VBIL0 ]-bit. NTSC default values and typical setups of 625 Component signals are
shown in the table below.
525 System
625 System
[VBIL4:VBIL0]-bit
Composite
Y/C
Component
Betacam
MII
Component
0x14 Default
0x18
(20-Decimal)
(24-Decimal)
Line1 ~ Line20
Line623.5 ~ Line625
VBI-Line
Line263.5 ~ Line283.5
Line1 ~ Line22.5
(from 430th pixedl of Line-263 to 429th pixel of Line-283)
Line311 ~ Line335
The VBI start line period for 625 Component Video is Line 624.
The VBI period of Field –2 is given as :
For 525 system, from 264 ( fixed value ) to ( set-value ) + 245.
For 625 system,from 311 ( fixed value ) to ( set value ) + 311.
TRSVSEL-bit is the control bit that specifies the V-bit in the REC. 656 EAV/SAV code.
This bit is set by [ VBIL4 : VBIL0 ] and is not affected by VBI period as shown below.
* < V-bit value in Rec.656 TRS and the line relationship >
NTSC(525 System)
625 System
Composite/YC/Component(MII,Betacam)
Component (EBU N10)
V-bit
TRSVSEL=0
TRSVSEL=1
TRSVSEL=0
TRSVSEL=1
V-bit = 0
Line10 ~ Line263
Line273 ~ Line525
Line20 ~ Line263
Line283 ~ Line525
Line23 ~ Line310
Line336 ~ Line623
V-bit = 1
Line1 ~ Line9
Line264 ~ Line272
Line1 ~ Line19
Line264 ~ Line282
Line1 ~ Line22
Line311 ~ Line335
Line624 ~ Line625
note) TRSVSEL-bit setting is as shown above. It is not affected by [ VBIL4 : VBIL0 ]-bit.
TRSVSEL-bit setting is shown above for all modes of 525/625 systems.
Rev.0
52
2003/01