AK8850 Datasheet, PDF (77/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
CLAMP CONTROL REGISTER ( R / W ) [ SUB ADDRESS 0x0A ]
This register controls clamp-related matters. Reserved bits must be set to “ 0 “.
Sub Address 0x0A
bit 7
bit 6
UNMASK Reserved
0
0
bit 5
ACLMP
0
bit 4
Bit 3
INCLPTMG FBCLPTMG1
Default Value
0
0
bit 2
FBCLPTMG0
0
Default Value : 0x00
bit 1
bit 0
CLPLVL1 CLPLVL0
0
0
Clamp Control Register
BIT Register Name
bit 0 CLPLVL0
~
bit 1 CLPLVL1
CLAMP Level 0
~
CLAMP Level1 bit
R/W Definition
Setting analog video clamp. This setting is valid
for Clamp 1. The level of Clamp 2/3 is constant
at 512 level.
R/W ^{CLPLVL1 CLPLVL0}
00: 16 [default]
01: 240
10: 252
11: Analog clamp is off
Setting the clamp timing pulse.
bit 2 FBCLPTMG0
~
bit 3 FBCLPTMG1
bit 4 INCLPTMG
bit 5
ACLAMP
bit 6 Reserved
bit 7 UNMASK
Feed Back Clamp Timing bit
Input Clamp Timing bit
Analog Clamp On/Off bit
Reserved bit
Clamp Unmask bit
00 : Synctip level clamp with the internal clamp
timing [default]
R/W
01 : Synctip level clamp with the external clamp
timing pulse.
10 : Pedestal level clamp with the internal clamp
timing pulse.
11 : Pedestal level clamp with the external clamp
timing pulse.
Setting the clamp timing pulse.
0 : Internal Clamp timing pulse [default]
1 : External Clamp timing pulse
Setting the clamp on/off.
When a video signal is input through AC
coupling capacitor, this set must be set to “0”.
R/W _{0 : ON [default]}
1 : OFF (AIN Clamp OFF)
R/W Reserved
Clamp mask on/off bit.
R/W ^{Normally this bit set to 0.}
0 : Masked [default]
1 : Unmasked
Rev.0
77
2003/01