AK8850 Datasheet, PDF (37/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
( 2 ) INPUT SIGNAL CLAMP FUNCTION
This function clamps the input signal to a proper level. The circuit clamps the SYNC-TIP level of input signal to
approximately 0.7 V. The input signal is clamped at the position as shown below.
The clamp timing pulse is controlled by either the internal Sync-separation circuit or by an externally-fed clamp timing
pulse via EXTCLP pin ( please refer to SYNC-TIP clamp timing pulse item ).
Clamp Level
Clamp timing
( 2-1 ) INPUT CLAMP CONTROL REGISTER:
* INPUT SIGNAL CLAMP ON /OFF BIT : ACLAMP-bit ( bit-3 )
ACLAMP
Function
0
Clamp ON (default)
1
Clamp OFF
The Input signal clamp function can be turned –off, for example, when DC signals are input..
Set ACLAMP=0 ( ON ) for normal operation.
( 3 ) ANALOG CLAMP FUNCTION
This function clamps the input signal using analog signal processing for a higher degree of precision, enabling
SYNC-TIP to be clamped to approximately 0.7 V by the input signal clamping.
Either of the SYNC-TIP clamp or the Pedestal clamp is selectable by the [ CLAMP CONTROL REGISTER ]. Clamp
timing is controlled by a clamp pulse that is generated by an internal Sync-separation circuit. It is also possible to control
it with an external signal connected to the EXTCLP pin. Either the SYNC-TIP clamp or the Pedestal clamp must be
selected and its clamp level set by [ CLPLVL 1 : CLPLVL 0 ]-bit.
If an internal clamp pulse is used, the selected clamp pulse can be output on the EXTCLP pin. When the C signal and
Pb / Pr component signals are input, the clamp levels of CLAMP2 / CLAMP3 are set to fixed values.
( 3-1 ) CLAMP CONTROL REGISTER DESCRIPTION
Clamp function is set by [ CLAMP CONTROL REGISTER ].
* [ CLAMP CONTROL REGISTER ]
bit 7
bit 6
bit 5
CLPMASK Reserved ACLAMP
0
0
0
bit 4
bit 3
INCLPTMG FBCLPTMG1
Default Value
0
0
bit 2
FBCLPTMG0
0
bit 1
CLPLVL1
0
bit 0
CLPLVL0
0
[CLPLVL1: CLPLVL0]-bit
(bit1:bi0)
[00]
Clamp level
Synctip
[01]
Pedestal
[10]
Pedestal
[11]
Clamp OFF
Note
Clamped at synctip level.
When internal clamp pulse is used, set to this mode
Clamped at Pedestal Level
For 286mV Sync levels and Analog Pedestal Clamp settings, use this mode.
286mV Sync : NTSC Composite , Y/C signal , Betacam Component
Clamped at Pedestal Level
For 300mV Sync level and Analog Pedestal Clamp settings, use this mode.
300mV Sync : 625 Component, MIIComponent
Analog clamp function is off
The control clamp timing is done by setting the clamp pulse timing [ CLPTMG 1 : CLPTMG 0 ]-bit.
Rev.0
37
2002/01