AK8850 Datasheet, PDF (17/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
5. Output Signal Timing Description
5-1. NTSC Input
Vertical Sync timing, Field signal and Frame signal timing relations are shown below. The logic states of HSYNC/VSYNC/FIELD/FRAME can be altered via register settings. Depending
on the register setting either VSYNC or VD signal is available. FIELD output and FRAME output signals change states on the rising edge of CSYNC just before the 0.5H delay period that
is controlled by the Output Control Register. The 0.5H delay timing is shown on page 18.
CSYNC
52
52
52
1
2
3
HSYNC
VSYNC
VD
FIELD
FRAME
EVEN
4
5
6
7
8
9
ODD
10
11
CSYNC
HSYNC
26
26
26
26
26
26
26
26
26
27
27
27
27
27
VSYNC
VD
FIELD
ODD
FRAME ^(Low)
EVEN
CSYNC
52
52
HSYNC
VSYNC
VD
FIELD
FRAME
52
1
EVEN
2
3
4
5
6
7
8
9
ODD
10
11
CSYNC
HSYNC
26
26
26
26
26
26
26
26
26
27
27
27
27
27
VSYNC
VD
ODD
FIELD
EVEN
FRAME _(High
Note)
Frame timing signal output is as shown above when standard signals are input to the AK8850. If a Non-standard signal is input to AK8850, the number of Color frame is not guaranteed. When the
input signal changes from non-standard to standard, that the Frame timing signal may not change for 512 lines (max) as the AK8850 synchronizes to the input video signal.
Rev.0
17
2002/0