AK8850 Datasheet, PDF (69/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
8. REGISTER DEFINITION
The AK8850 has the following registers.
Sub
Address
Register
0x00 Input Video Standard Register
0x01 Input Signal Select Register
0x02 Vertical Blanking Length Register
0x05 Output Control Register
0x06 Output Format Register
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
Control-1 Register
Control-2 Register
Clamp Control Register
Clamp Timing Control Register
Clamp Timing 2 Control Register
PGA1 Gain Control Register
PGA2 Gain Control Register
PGA3 Gain Control Register
Y/C Separation Control Register
Color Killer Control Register
Brightness Control Register
Contrast Control Register
Saturation Control Register
HUE Control Register
0x1C Power Save Register
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2E
Request VBI Info Register
Status 1 Register
Status 2 Register
Closed Caption1 Register
Closed Caption2 Register
Extended Data 1 Register
Extended Data 2 Register
VBID1 Register
VBID2 Register
WSS1 Register
WSS2 & Aspect Data Register
Device/Revision ID Register
0x36
0x37
0x38
0x39
0x3A
0x46
0x47
Clock Control-1 Register
Clock Control-2 Register
Clock Control-3 Register
Clock Control-4 Register
Clock Control-5 Register
PLL Control Register
PLL DAC Set Register
Default
0x00
0x11
0x14
R/W
R/W
R/W
R/W
Function
Set Input Video Standard
Select Input Video signal
Set VBI Interval
0x14 R/W Set the attribution of output data
0x00 R/W Set the output I/F
0x80 R/W Control Register
0xC1 R/W Control Register
0x00 R/W Set the clamp function setting
0x11 R/W Set the clamp pulse timing
0x1C
Set the clamp pulse timing
0x40 R/W Set the manual Gain of PGA1
0x40 R/W Set the manual Gain of PGA2
0x40 R/W Set the manual Gain of PGA3
0x06 R/W Set the YC Separation function
0xAD R/W Color killer setting
0x00 R/W Set Brightness adjustment
0x80 R/W Set Contrast adjustment
0x80 R/W Set Saturation adjustment
0x00 R/W Set HUE adjustment
0x00 R/W Power Save setting
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
W VBIDdata decode requet
R Internal status of AK8850
R nternal status of AK8850
R Closed Caption data
R Closed Caption data
R Closed Caption Extended data
R Closed Caption Extended data
R VBID data
R VBID data
R WSS data
R WSS data and video aspect data.
R Device ID / Revision ID
0x84
0x7C
0x3C
0xDC
0x04
0x00
0x80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock transition control register.
Clock transition control register.
Clock transition control register.
Clock transition control register.
Clock transition control register.
PLL Control Register
PLL_DAC Setting register
[AK8850]
Rev.0
69
2003/01