AK8850 Datasheet, PDF (78/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
CLAMP TIMING 1 CONTROL REGISTER ( R / W ) [ SUB ADDRESS 0x0B ]
This register sets SYNC-TIP Clamp timing. Clamp Timing Pulse generation and its pulse width can be adjusted.
Output signal mode selection of the EXTCLP pin is also possible. For a timing diagram, refer to the SYNC Separation
description in the Clamp section. Reserved bits must be set to “ 0 “.
Sub Address 0x0B
bit 7
bit 6
EXTCLP1 EXTCLP0
0
0
bit 5
SCLPWIDTH2
0
bit 4
bit 3
SCLPWIDTH1 SCLPWIDTH0
Default Value
1
0
bit 2
SCLPSTAT2
0
Default Value : 0x11
bit 1
bit 0
SCLPSTAT1 SCLPSTAT0
0
1
Clamp Timing Control Register
BIT Register Name
bit 0 SCLPSTAT0
Synctip Clamp Start timing0
bit 2 SCLPSTAT2 Synctip Clamp Start timing2 bit
R/W Definition
Setting the start position of synctip clamp pulse
R/W
default value is
SCLPSTA2 : SCLPSTA0 = 001
bit 3 SCLPWIDTH0
Synctip Clamp Pulse Width0 bit
[SCLPSTAT2 SCLPSTAT0 ]
000 : 2clks later
001 : 4clks later
010 : 6clks later
011 : 8clks later
100 : 10clks later
101 : 12clks later
110 : 14clks later
111 : 16clks later
1clk is about 37[nsec]
R/W Setting the synctip clamp pulse width
Default value is
SCLPWIDTH2 : SCLPWIDTH0 = 010.
bit 5 SCLPWIDTH2 Synctip Clamp Pulse Width2 bit
[SCLPWIDTH3 SCLPWIDTH0]
000 : 2 clks (74nsec)
001 : 4 clks (148nsec)
010 : 8 clks (296nsec)
011 : 16 clks (592nsec)
100 : 24 clks (888nsec)
101 : 32 clks (1.18usec)
110 : 40 clks (1.48usec)
111 :48 clks (1.78usec)
bit 6 EXTCLP0
External Clamp 0 bit
R/W Setting the output the timing data from
EXTCLP-pin.
bit 7 EXTCLP1
External Clamp 1 bit
[EXTCLP1:EXTCLP0]
00 : Hi-Z (Defaul)
01 : Internal synctip clamp timing pulse.
10 : Internal pedestal clamp timing pulse.
11 : SYNCDET signal
Rev.0
78
2003/01