AK8850 Datasheet, PDF (75/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
CONTROL 1 REGISTER / CONTROL 2 REGISTER
These registers control the AK8850 operations.
There are 2 registers, CONTROL 1 and CONTROL 2. Reserved bits must be set to “ 0 “.
Control 1 Register (R/W) [Sub Address 0x08]
Sub Address 0x08
bit 7
bit 6
FRCSYNC Reserved
1
0
bit 5
INTPOL1
0
bit 4
bit 3
INTPOL0
AGCC1
Default Value
0
0
bit 2
AGCC0
0
Default Value : 0x80
bit 1
bit 0
AGCT1
AGCT0
0
0
Control 1 Register Definition
BIT Register Name
bit 0
AGCT0
~
~
AGC Time Constant Control bits
bit 1
AGCT1
bit 2
AGCC0
AGC Coring Control bits
~
~
bit 3
AGCC1
bit 4 INTPOL0 Interpolator Control bit
~
bit 5 INTPOL1
R/W Definition
Set the AGC time constant.
When the AGC is Disabled, each PGA can be
set manually.
R/W [AGCT1 AGCT0] =
00 : Disable [default]
01 : Fast [T = 1Field]
10 : Middle [T = 7Field]
11 : Slow [T = 29Field]
(T : Time constance)
Set the non-sensing bandwidth of AGC
R/W [AGCC1 AGCC0] =
00 : No non-sensing bandwidth[Default]
01 : 1bit
10 : 2bits
11 : 3bits
Setting for Pixel Interpolator
R/W [INTPOL1 INTPOL0] =
00 : Auto [Default ]
01 : ON
10 : OFF
11 : Reserved
bit 6 Reserved Reserved
bit 7 FRCSYNC Frame CSYNC switch bit
Setting to Automode, the Interpolator switch
turns on/off according to the clock mode as
described bellow,
Line Lock PLL :
OFF
Frame Lock PLL: ON
Fixed Clock mode: ON
R/W Reserved
R/W Define the output data from FRAME1pin.
0 : FRAME timing pulse output
1 : CSYNC timing pulse output [default]
Rev.0
75
2003/01