AK8850 Datasheet, PDF (79/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
CLAMP TIMING 2 CONTROL REGISTER ( R / W ) [ SUB ADDRESS 0x0C ]
This register sets the Pedestal Clamp timing.
The timing of the Clamp Timing Pulse generation and its pulse width can be adjusted.
For timing diagram,refer to the SYNC-Separation description in the Clamp section. Reserved bits must be set to “ 0 “.
Sub Address 0x0C
bit 7
bit 6
SLCLV1
SLCLV0
0
0
bit 5
PCLPWIDTH2
0
bit 4
bit 3
PCLPWIDTH1 PCLPWIDTH0
Default Value
1
1
bit 2
PCLPSTAT2
1
Default Value :0x1C
bit 1
bit 0
PCLPSTAT1 PCLPSTAT0
0
0
CLAMP Timing 2 Control Register
BIT Register Name
R/W Definition
Setting the start position of pedestal clamp
pulse.
default value is
PCLPSTA2 : PCLPSTA0 = 100
[PCLPSTAT2 PCLPSTAT0]
Pedestal Clamp Start timing0 bit
bit 0 _PCLPSTAT0
000 : 118 clks (4.37usec) later
001 : 126 clks (4.65usec) later
bit 2 _PCLPSTAT2
Pedestal Clamp Start timing2
bit
R/W 010 : 132 clks (4.88usec) later
011 : 140 clks (5.18usec) later
100 : 148 clks (5.48usec) later
101 : 156 clks (5.77usec) later
110 : 164 clks (6.07usec) later
111 : 172 clks (6.36usec) later
1clk is about 37[nsec]
Setting the pedestal clamp timing pulse width.
Default value is
PCLPWIDTH2 : PCLPWIDTH0 = 011
bit 3 PCLPWIDTH0
bit 5 PCLPWIDTH3
bit 6
SLCLV0
bit 7
SLCLV1
Pedestal Clamp Pulse Width0
Pedestal Clamp Pulse Width3
bit
Slice Level Control bit
[PCLPWIDTH3 PCLPWIDTH0]
000 : 16 clks (592 nsec)
R/W 001 : 24 clks (888 nsec)
010 : 28 clks (1.04 usec)
011 : 32 clks (1.18 usec)
100 : 40 clks (1.48 usec)
101 : 44 clks (1.63 usec)
110 : 48 clks (1.78 usec)
111 : 52 clks (1.92 usec)
Setting the slice level
Default value is 00
[SLCLV1:SLCLV0] =
R/W 00 :Sliced 1/4 level above the synctip
01 :Sliced 1/2 level above the synctip
10 :Prohibit to set
11: Sliced 3/8 level above the synctip
Rev.0
79
2003/01