AK8850 Datasheet, PDF (94/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
PLL CONTROL REGISTER ( R / W ) [ SUB ADDRESS 0x46 ]
PLL control register.
Sub Address 0x46
bit 7
bit 6
Reserved LPGAUTO
0
0
bit 5
LPG3
0
bit 4
bit 3
LPG2
LPG1
Default Value
0
0
bit 2
LPG0
0
Default Value : 0x00
bit 1
bit 0
LPGM1
LPGM2
0
0
PLL Control Register Definition
BIT Register Name
bit 0 LPGM2:LPGM Loop Gain Control bit
1
bit 1
bit 2
LPG0:LPG3 Loop Gain Control bit
bit 5
bit 6 LPGAUTO Loop Gain Auto bit
R/W Definition
R/W FRAME LOCK Mode EC gain
LPGM[1:2] =
00 : x 1 (Default
01 : x 2
10 : x 4
11 : x 8
LPG[1:0] Line Lock mode EC gain[1:0]
00 : x 1 (Default
01 : x 1/2
10 : x 4
11 : x 2
R/W LPG[2] CP gain
0 : x 1 (Default
1:x2
LPG[3] GM gain
0 : x 1 (Default)
1:x2
R/W 0 : Manual Default
1 : Auto
bit 7 Reserved
Reserved bit
In case of Auto mode setting, LPG2 and LPG3
settings are ignored and the CP and GM gains
are switched automatically depending on the
PLL mode.
Line-Lock mode:
CP x 1 (Low), GM : x1 (Low)
Frame-Lock mode :
CP : x 2 (High) , GM : x 2 (High)
R/W Reserved
Rev.0
94
2003/01