AK8850 Datasheet, PDF (93/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
CLOCK CONTROL- 3 REGISTER ( R / W ) [ SUB ADDRESS 0x38 ]
This register controls the Clock Transition time in Auto Clock mode which is set by [ bit 7 : bit 6 ] of the Auto Select
Control 2 Register ( 0x09 ).
Sub Address 0x38
bit 7
bit 6
FRLNTH7 FRLNTH6
0
0
bit 5
FRLNTH5
1
bit 4
bit 3
FRLNTH4 FRLNTH3
Default Value
1
1
bit 2
FRLNTH2
1
Default Value : 0x3C
bit 1
bit 0
FRLNTH1 FRLNTH0
0
0
Clock Control 3 Register Definition
BIT Register Name
R/W Definition
bit 0 FRLNTH0 Frame to Line Threshold Level R/W The threshold parameter from Frame-Lock clock
~
Control bit
mode to Line-Lock clock mode.
bit 7 FRLNTH7
CLOCK CONTROL-4 REGISTER ( R / W ) [ SUB ADDRESS : 0x39 ]
This register controls the Clock Transition time in Auto Clock mode which is set by [ bit 7 : bit 6 ] of the Auto Select Control
2 Register ( 0x09 ).
Sub Address 0x39
bit 7
bit 6
FRFXTH7 FRFXTH6
1
1
bit 5
FRFXTH5
0
bit 4
bit 3
FRFXTH4 FRFXTH3
Default Value
1
1
bit 2
FRFXTH2
1
Default Value : 0xDC
bit 1
bit 0
FRFXTH1 FRFXTH0
0
0
Clock Control 4 Register Definition
BIT Register Name
R/W Definition
bit 0 FRFXTH0 Frame to Fix Clock Threshold R/W The threshold parameter from Frame-Lock clock
~
Level Control bit
mode to Fixed clock mode.
bit 7 FRFXTH7
CLOCK CONTROL-5 REGISTER ( R / W ) [ SUB ADDRESS 0x3A ]
This register controls the Clock Transition time in clock Auto Mode set by ( bit 7 : bit 6 ) of the Auto Select Control 2
Register ( 0x09 ).
Sub Address 0x3A
Default Value : 0x04
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FXLNTH7 FXLNTH6 FXLNTH5 FXLNTH4 FXLNTH3 FXLNTH2 FXLNTH1 FXLNTH0
Default Value
0
0
0
0
0
1
0
0
Clock Control 5 Register Definition
BIT Register Name
R/W Definition
bit 0 FXLNTH0 Fix Clock to Line Threshold R/W The threshold parameter for switching between
~
Level Control bit
the Fixed clock and Line-Lock clock modes.
bit 7 FXLNTH7
Rev.0
93
2003/01