AK8850 Datasheet, PDF (36/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
The Pedestal clamp timing pulse at the default state generates a clamp pulse as shown in the following timing diagram.
Video signal Input
Position of HSYNC
(AIN1/AIN2/AIN3)
After LPF
SYNC1/2/3 input
HSYNC
After Sync Separation
Internal Sync Reference
(SYNCDET)
Pedestal clamp
timing pulse
5.3usec
2.5usec
4.92usec=133[clk]
380nsec
70mV
[PCLPSTA3: PCLPSTA0]-bit Clocks
( Default 5.48usec = 148 [clk] )
Default value is 21 cycles
1Clock = 37nsec
[PCLPWIDTH3: PCLPWIDTH0]-bit Clocks
Default Pedestal clamp timing
( 1-6-5 ) CLAMP TIMING PULSE MASK FUNCTION
The Clamp timing pulse generation is masked at the default state to avoid mis-clamping outside the SYNC signal timing.
This masking function can be disabled.
* [ CLAMP CONTROL REGISTER ] set is done by UNMASK-bit
UNMASK-bit
Function
0
Masked
1
Un-Masked
For typical use,please set UNMASK bit =0.
default
Rev.0
36
2002/01