AK8850 Datasheet, PDF (64/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
* [ OUTPUT CONTROL REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
VDVSYNC FFDELAY HALFCLK FRAME DVALVLK
FEILD
VSYNC
Default Value
0
0
0
1
0
1
0
Logical state can be altered by these registers. Default value is “ 0 “ as shown in the timing diagram.
* [ CONTROL 1 REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
FRCSYNC DECIMAT INTPOL1 INTPOL0 AGCC1
Default Value
1
0
0
0
0
FRCSYNC-bit controls output on FRAME 1 pin.
bit 2
AGCC0
0
bit 1
AGCT1
0
bit 0
HSYNC
0
bit 0
AGCT0
0
7-4-20 VLOCK FUNCTION
The AK8850 synchronizes its internal operation with the input signal’s FRAME configuration. For example, if the input
signal Frame configuration consists of 525 lines, the internal operation uses the 525 Line configuration. This is called the
VLOCK configuration.
When the input signal configured with 525 Line per Frame is switched to 524 Lines, the operation tracks to the switched
input signal system.
In this case VLOCK function is put into un-locked state during the tracking time. The un-locked state is verified by the
[ STATUS 1 REGISTER ].
VLOCK status is observed on the DVALID pin by setting the DVAL / VLK-bit of the [ OUTPUT CONTROL REGISTER ] ( R
/ W ) [ SUB ADDRESS 0x05 ].
VLOCK Status
Locked (synchronaize with Input video signal)
UnLocked Un-synchronaized with input video signal
Status 1 Register
VLOCK-bit
1
0
VLOCK output pin
High
Low
The transition timing of the VLOCK output pin changes with VLOCK configuration conditions. .
Rev.0
64
2003/01