AK8850 Datasheet, PDF (85/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
POWER SAVE REGISTER ( R / W ) [ SUB ADDRESS : 0x1C ]
Controls the transition to Power Save mode. Recovery from the Power Save mode is done by writing “ 0 “ to PS-bit.
Sub Address 0x1C
bit 7
bit 6
Reserved Reserved
bit 5
Reserved
0
0
0
Power Save Register Definition
BIT Register Name
bit 0
PS
Power Save bit
bit 1
ADC1
AD1 Save bit
bit 2
ADC2
ADC2 Save bit
bit 3
ADC3
ADC3 Save bit
bit 4
PLLRST
PLL Reset bit
bit 5
Reserved Reserved bit
bit 7
bit 4
bit 3
PLLRST
ADC3
Default Value
0
0
bit 2
ADC2
0
Default Value : 0x00
bit 1
bit 0
ADC1
PS
0
0
R/W
R/W
R/W
R/W
R/W
Definition
Power Save Mode setting register bit
0 : Switch to the Active mode from the Power
Save Mode
1 : Switch to the Power Save Mode
Power save mode for ADC1
0 : Switch to the Active mode
1 : Switch to the Power save mode
Power save mode for ADC2
0 : Switch to the Active mode
1 : Switch to the Power save mode
Power save mode for ADC3
0 : Switch to the Active mode
1 : Switch to the Power save mode
Reset the PLL control Circuit.
Set to “1 “ and set to “0” after setting “1”.
R/W
Reserved
Rev.0
85
2003/01