AK8850 Datasheet, PDF (33/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
Monitor pulse is selected as follows.
[EXTMON1:EXTMON0]-bit
Monitor source
00
High Impedance ( Unavailable monitoring)
01
Internal Synctipu clamp timing pulse
10
Internal pedestal clamp timing pulse
11
SYNCDET pulse
Note
Default
( 1-6-3 ) SYNC-TIP CLAMP TIMING PULSE SET
When using the internal SYNC-TIP clamp timing pulse for clamp functions, set the start position and pulse width of the
SYNC-TIP clamp timing pulse using the [ CLAMP TIMING1 CONTROL REGISTER ].This setting is valid only when the
[ INCLPTMG : FBCLPTMG1 : FBCLPTMG0 ]-bits are set to use the internal clamp pulse for SYNC-TIP clamping ( it is
invalid if external clamp pulse is used ).
To monitor the clamp pulse timing generated by the internal clamp circuit, ensure that [ EXTMON1 : EXTMON0 ]-bit of
the [ CLAMP TIMING1 CONTROL REGISTER ] is properly set.
The slice level is adjustable by setting [ SLCLV 1 : SLCLV 0 ]-bit of the [ CLAMP TIMING 2 CONTROL REGISTER ].
* [ CLAMP TIMING1 CONTROL REGISTER ]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EXTMON1 EXTMON0 SCLPWIDTH2 SCLPWIDTH1 SCLPWIDTH0 SCLPSTAT2 SCLPSTAT1 SCLPSTAT0
Default Value
0
0
0
0
0
0
Start position of the Analog SYNC-TIP clamp timing pulse is set by [ SCLPSTA2 : SCLPSTAT0]-bit ,and the clamp pulse
width is adjusted using the [ SCLPWIDTH3 : SCLPWIDTH0 ]-bit.
* When [ SCLPSTA2 : SCLPSTAT0 ]-bit and [ SCLPWIDTH3 : SCLPWIDTH0 ]-bit are valid, settings are as follows.
[INCLPTMG: FBCLPTMG1:FBCLPTMG0]-bit
monitor with EXTCLP
Note
[000]
Available
Internal Synctip clamp pulse
[010]
Available
internal Pedestal clamp timing Pulse
[011]
Unavailable
External Pedestal clamp timing pulse
SYNC-TIP clamp pulse related settings are shown below.
* SYNC-TIP clamp pulse start position set by [ SCLPSTAT2 : SCLPSTAT0 ]-bit
[SCLPSTAT2:SCLPSTAT0]-bit
Start position from the falling edge
of Synchronization pulse
000
Passed after 0-Clocks (0nsec)
001
Passed after 2-Clocks (74nsec)
010
Passed after 4-Clocks (148nsec)
Actual Clamp pulse timing position
Passed after 2-Clocks (74nsec)
Passed after 4-Clocks (148nsec)
Passed after 6-Clocks (222nsec)
011
Passed after 6-Clocks (222nsec) Passed after 8-Clocks (296nsec)
100
Passed after 8-Clocks (296nsec) Passed after 10-Clocks (370nsec)
101
Passed after 10-Clocks (370nsec) Passed after 12-Clocks (444nsec)
110
Passed after 12-Clocks (444nsec) Passed after 14-Clocks (481nsec)
111
Passed after 14-Clocks (518nsec) Passed after 16-Clocks (592nsec)
[ SCLPSTAT2 : SCLPSTAT0 ]-bit is used to fine-tune the start position whose default value is [001], or 2 clocks (74ns).
The clamp start position is adjusted with the [ SCLPSTAT2 : SCLPSTAT0 ]-bit as follows. The actual clamping position
occurs 2 clock cycles after sync pulse is generated..
Rev.0
33
2002/01