DS891 Datasheet, PDF (9/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Table 6: Zynq UltraScale+ MPSoC: EV Device-Package Combinations and Maximum I/Os
Package
(1)(2)(3)(4)
Package
Dimensions
(mm)
SFVC784⁽⁵⁾
23x23
FBVB900
31x31
FFVC1156
35x35
FFVF1517
40x40
ZU4EV
HD, HP
GTH, GTY
96, 156
4, 0
48, 156
16, 0
ZU5EV
HD, HP
GTH, GTY
96, 156
4, 0
48, 156
16, 0
ZU7EV
HD, HP
GTH, GTY
48, 156
16, 0
48, 312
20, 0
48, 416
24, 0
Notes:
1. Go to Ordering Information for package designation details.
2. FB/FF packages have 1.0mm ball pitch. SF packages have 0.8mm ball pitch.
3. All device package combinations bond out 4 PS-GTR transceivers.
4. Packages with the same last letter and number sequence, e.g., C784, are footprint compatible with all other UltraScale
devices with the same sequence. The footprint compatible devices within this family are outlined.
5. GTH transceivers in the SFVC784 package support data rates up to 12.5Gb/s.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
9