DS891 Datasheet, PDF (23/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Interconnect
All the blocks are connected to each other and to the PL through a multi-layered ARM Advanced
Microprocessor Bus Architecture (AMBA) AXI interconnect. The interconnect is non-blocking and supports
multiple simultaneous master-slave transactions.
The interconnect is designed with latency sensitive masters, such as the ARM CPU, having the shortest
paths to memory, and bandwidth critical masters, such as the potential PL masters, having high
throughput connections to the slaves with which they need to communicate.
Traffic through the interconnect can be regulated through the Quality of Service (QoS) block in the
interconnect. The QoS feature is used to regulate traffic generated by the CPU, DMA controller, and a
combined entity representing the masters in the IOP.
PS Interfaces
PS interfaces include external interfaces going off-chip or signals going from PS to PL.
PS External Interfaces
The Zynq UltraScale+ MPSoC’s external interfaces use dedicated pins that cannot be assigned as PL pins.
These include:
• Clock, reset, boot mode, and voltage reference
• Up to 78 dedicated multiplexed I/O (MIO) pins, software-configurable to connect to any of the internal I/O
peripherals and static memory controllers
• 32-bit or 64-bit DDR4/DDR3/DDR3L/LPDDR3 memories with optional ECC
• 32-bit LPDDR4 memory with optional ECC
• 4 channels (TX and RX pair) for transceivers
MIO Overview
The IOP peripherals communicate to external devices through a shared pool of up to 78 dedicated
multiplexed I/O (MIO) pins. Each peripheral can be assigned one of several pre-defined groups of pins,
enabling a flexible assignment of multiple devices simultaneously. Although 78 pins are not enough for
simultaneous use of all the I/O peripherals, most IOP interface signals are available to the PL, allowing use
of standard PL I/O pins when powered up and properly configured. Extended multiplexed I/O (EMIO) allows
unmapped PS peripherals to access PL I/O.
Port mappings can appear in multiple locations. For example, there are up to 12 possible port mappings
for CAN pins. The PS Configuration Wizard (PCW) tool aids in peripheral and static memory pin mapping.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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