DS891 Datasheet, PDF (29/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
3-State Digitally Controlled Impedance and Low Power I/O Features
The 3-state Digitally Controlled Impedance (T_DCI) can control the output drive impedance (series
termination) or can provide parallel termination of an input signal to V_CCO or split (Thevenin) termination
to V_CCO/2. This allows users to eliminate off-chip termination for signals using T_DCI. In addition to board
space savings, the termination automatically turns off when in output mode or when 3-stated, saving
considerable power compared to off-chip termination. The I/Os also have low power modes for IBUF and
IDELAY to provide further power savings, especially when used to implement memory interfaces.
I/O Logic
Input and Output Delay
All inputs and outputs can be configured as either combinatorial or registered. Double data rate (DDR) is
supported by all inputs and outputs. Any input or output can be individually delayed by up to 1,250ps of
delay with a resolution of 5–15ps. Such delays are implemented as IDELAY and ODELAY. The number of
delay steps can be set by configuration and can also be incremented or decremented while in use. The
IDELAY and ODELAY can be cascaded together to double the amount of delay in a single direction.
ISERDES and OSERDES
Many applications combine high-speed, bit-serial I/O with slower parallel operation inside the device. This
requires a serializer and deserializer (SerDes) inside the I/O logic. Each I/O pin possesses an IOSERDES
(ISERDES and OSERDES) capable of performing serial-to-parallel or parallel-to-serial conversions with
programmable widths of 2, 4, or 8 bits. These I/O logic features enable high-performance interfaces, such
as Gigabit Ethernet/1000BaseX/SGMII, to be moved from the transceivers to the SelectIO interface.
High-Speed Serial Transceivers
Ultra-fast serial data transmission between devices on the same PCB, over backplanes, and across even
longer distances is becoming increasingly important for scaling to 100 Gb/s and 400 Gb/s line cards.
Specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity
issues are required at these high data rates.
Three types of transceivers are used in Zynq UltraScale+ MPSoCs: GTH, GTY, and PS-GTR. All transceivers
are arranged in groups of four, known as a transceiver Quad. Each serial transceiver is a combined
transmitter and receiver. Table 10 compares the available transceivers.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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