DS891 Datasheet, PDF (4/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Feature Summary
Table 1: Zynq UltraScale+ MPSoC: CG Device Feature Summary
ZU2CG
ZU3CG
ZU4CG
ZU5CG
ZU6CG
ZU7CG
ZU9CG
Application Processing Unit
Dual-core ARM Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision Floating Point;
32KB/32KB L1 Cache, 1MB L2 Cache
Real-Time Processing Unit
Dual-core ARM Cortex-R5 with CoreSight; Single/Double Precision Floating Point; 32KB/32KB L1
Cache, and TCM
Embedded and External
Memory
256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3;
External Quad-SPI; NAND; eMMC
General Connectivity
214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; WatchDog Timers; Triple
Timer Counters
High-Speed Connectivity
4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII
System Logic Cells
103,320
154,350
192,150
256,200
469,446
504,000
599,550
CLB Flip-Flops
94,464
141,120
175,680
234,240
429,208
460,800
548,160
CLB LUTs
47,232
70,560
87,840
117,120
214,604
230,400
274,080
Distributed RAM (Mb)
1.2
1.8
2.6
3.5
6.9
6.2
8.8
Block RAM Blocks
150
216
128
144
714
312
912
Block RAM (Mb)
5.3
7.6
4.5
5.1
25.1
11.0
32.1
UltraRAM Blocks
0
0
48
64
0
96
0
UltraRAM (Mb)
0
0
14.0
18.0
0
27.0
0
DSP Slices
240
360
728
1,056
1,973
1,728
2,520
CMTs
Max. HP I/O⁽¹⁾
Max. HD I/O⁽²⁾
3
3
4
4
4
8
4
156
156
156
156
208
416
208
96
96
96
96
120
48
120
System Monitor
2
GTH Transceiver 16.3Gb/s⁽³⁾
0
2
2
2
2
2
2
0
16
16
24
24
24
GTY Transceivers 32.75Gb/s
0
0
0
0
0
0
0
Transceiver Fractional PLLs
0
0
8
8
12
12
12
PCIe Gen3 x16 and Gen4 x8
0
0
2
2
0
2
0
150G Interlaken
0
0
0
0
0
0
0
100G Ethernet w/ RS-FEC
0
0
0
0
0
0
0
Notes:
1. HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V.
2. HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V.
3. GTH transceivers in the SFVC784 package support data rates up to 12.5Gb/s. See Table 2.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
4