DS891 Datasheet, PDF (7/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Table 4: Zynq UltraScale+ MPSoC: EG Device-Package Combinations and Maximum I/Os
Package
(1)(2)(3)(4)(5)
Package
Dimensions
(mm)
ZU2EG
HD, HP
GTH, GTY
ZU3EG
HD, HP
GTH, GTY
ZU4EG
HD, HP
GTH, GTY
ZU5EG
HD, HP
GTH, GTY
ZU6EG
HD, HP
GTH, GTY
ZU7EG
HD, HP
GTH, GTY
ZU9EG
HD, HP
GTH, GTY
ZU11EG
HD, HP
GTH, GTY
ZU15EG
HD, HP
GTH, GTY
ZU17EG
HD, HP
GTH, GTY
ZU19EG
HD, HP
GTH, GTY
SBVA484⁽⁶⁾
19x19
24, 58
0, 0
24, 58
0, 0
SFVA625
21x21
24, 156
0, 0
24, 156
0, 0
SFVC784⁽⁷⁾
23x23
96, 156
0, 0
96, 156
0, 0
96, 156
4, 0
96, 156
4, 0
FBVB900
31x31
48, 156
16, 0
48, 156
16, 0
48, 156
16, 0
FFVC900
31x31
48, 156
16, 0
48, 156
16, 0
48, 156
16, 0
FFVB1156
35x35
120, 208
24, 0
120, 208
24, 0
120, 208
24, 0
FFVC1156
35x35
48, 312
20, 0
48, 312
20, 0
FFVB1517
40x40
72, 416
16, 0
72, 572
16, 0
72, 572
16, 0
FFVF1517
40x40
48, 416
24, 0
48, 416
32, 0
FFVC1760
42.5x42.5
96, 416
32, 16
96, 416
32, 16
96, 416
32, 16
FFVD1760
42.5x42.5
48, 260
44, 28
48, 260
44, 28
FFVE1924
45x45
96, 572
44, 0
96, 572
44, 0
Notes:
1. Go to Ordering Information for package designation details.⁽⁵⁾
2. FB/FF packages have 1.0mm ball pitch. SB/SF packages have 0.8mm ball pitch.
3. All device package combinations bond out 4 PS-GTR transceivers.
4. All device package combinations bond out 214 PS I/O except ZU2EG and ZU3EG in the SBVA484 and SFVA625 packages, which bond out 170 PS I/Os.
5. Packages with the same last letter and number sequence, e.g., A484, are footprint compatible with all other UltraScale devices with the same sequence. The footprint
compatible devices within this family are outlined.
6. All 58 HP I/O pins are powered by the same V_CCO supply.
7. GTH transceivers in the SFVC784 package support data rates up to 12.5Gb/s.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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