DS891 Datasheet, PDF (30/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Table 10: Transceiver Information
Type
Qty
Max. Data Rate
Min. Data Rate
Applications
PS-GTR
4
6.0Gb/s
1.25Gb/s
• PCIe Gen2
• USB
• Ethernet
Zynq UltraScale+ MPSoCs
GTH
GTY
0–44
0–28
16.3Gb/s
32.75Gb/s
0.5Gb/s
0.5Gb/s
• Backplane
• PCIe Gen4
• HMC
• 100G+ Optics
• Chip-to-Chip
• 25G+ Backplane
• HMC
The following information in this section pertains to the GTH and GTY only.
The serial transmitter and receiver are independent circuits that use an advanced phase-locked loop (PLL)
architecture to multiply the reference frequency input by certain programmable numbers between 4 and
25 to become the bit-serial data clock. Each transceiver has a large number of user-definable features and
parameters. All of these can be defined during device configuration, and many can also be modified
during operation.
Transmitter
The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 16, 20, 32, 40, 64,
or 80 for the GTH and 16, 20, 32, 40, 64, 80, 128, or 160 for the GTY. This allows the designer to trade off
datapath width against timing margin in high-performance designs. These transmitter outputs drive the
PC board with a single-channel differential output signal. TXOUTCLK is the appropriately divided serial
data clock and can be used directly to register the parallel data coming from the internal logic. The
incoming parallel data is fed through an optional FIFO and has additional hardware support for the
8B/10B, 64B/66B, or 64B/67B encoding schemes to provide a sufficient number of transitions. The
bit-serial output signal drives two package pins with differential signals. This output signal pair has
programmable signal swing as well as programmable pre- and post-emphasis to compensate for PC board
losses and other interconnect characteristics. For shorter channels, the swing can be reduced to reduce
power consumption.
Receiver
The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit-serial differential
signal into a parallel stream of words, each 16, 20, 32, 40, 64, or 80 bits in the GTH or 16, 20, 32, 40, 64, 80,
128, or 160 for the GTY. This allows the designer to trade off internal datapath width against logic timing
margin. The receiver takes the incoming differential data stream, feeds it through programmable DC
automatic gain control, linear and decision feedback equalizers (to compensate for PC board, cable,
optical and other interconnect characteristics), and uses the reference clock input to initiate clock
recognition. There is no need for a separate clock line. The data pattern uses non-return-to-zero (NRZ)
encoding and optionally ensures sufficient data transitions by using the selected encoding scheme.
Parallel data is then transferred into the device logic using the RXUSRCLK clock. For short channels, the
transceivers offer a special low-power mode (LPM) to reduce power consumption by approximately 30%.
The receiver DC automatic gain control and linear and decision feedback equalizers can optionally
“auto-adapt” to automatically learn and compensate for different interconnect characteristics. This
enables even more margin for tough 10G+ and 25G+ backplanes.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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