DS891 Datasheet, PDF (31/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Out-of-Band Signaling
The transceivers provide out-of-band (OOB) signaling, often used to send low-speed signals from the
transmitter to the receiver while high-speed serial data transmission is not active. This is typically done
when the link is in a powered-down state or has not yet been initialized. This benefits PCIe and SATA/SAS
and QPI applications.
Integrated Interface Blocks for PCI Express Designs
The MPSoC PL includes integrated blocks for PCIe technology that can be configured as an Endpoint or
Root Port, compliant to the PCI Express Base Specification Revision 3.1 for Gen3 and lower data rates and
compatible with the PCI Express Base Specification Revision 4.0 (rev 0.5) for Gen4 data rates. The Root Port
can be used to build the basis for a compatible Root Complex, to allow custom chip-to-chip
communication via the PCI Express protocol, and to attach ASSP Endpoint devices, such as Ethernet
Controllers or Fibre Channel HBAs, to the MPSoC.
This block is highly configurable to system design requirements and can operate 1, 2, 4, 8, or 16 lanes at
up to 2.5Gb/s, 5.0Gb/s, 8.0Gb/s, or 16Gb/s data rates. For high-performance applications, advanced
buffering techniques of the block offer a flexible maximum payload size of up to 1,024 bytes. The
integrated block interfaces to the integrated high-speed transceivers for serial connectivity and to block
RAMs for data buffering. Combined, these elements implement the Physical Layer, Data Link Layer, and
Transaction Layer of the PCI Express protocol.
Xilinx provides a light-weight, configurable, easy-to-use LogiCORE™ IP wrapper that ties the various
building blocks (the integrated block for PCIe, the transceivers, block RAM, and clocking resources) into an
Endpoint or Root Port solution. The system designer has control over many configurable parameters: link
width and speed, maximum payload size, MPSoC logic interface speeds, reference clock frequency, and
base address register decoding and filtering.
Integrated Block for Interlaken
Some UltraScale architecture-based devices include integrated blocks for Interlaken. Interlaken is a
scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10Gb/s to
150Gb/s. The Interlaken integrated block in the UltraScale architecture is compliant to revision 1.2 of the
Interlaken specification with data striping and de-striping across 1 to 12 lanes. Permitted configurations
are: 1 to 12 lanes at up to 12.5Gb/s and 1 to 6 lanes at up to 25.78125Gb/s, enabling flexible support for
up to 150Gb/s per integrated block. With multiple Interlaken blocks, certain UltraScale architecture-based
devices enable easy, reliable Interlaken switches and bridges.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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