DS891 Datasheet, PDF (39/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
PS Boot and Device Configuration
Zynq UltraScale+ MPSoCs use a multi-stage boot process that supports both a non-secure and a secure
boot. The PS is the master of the boot and configuration process. For a secure boot, the AES-GCM,
SHA-3/384 decrypts and authenticates the images while the 4096-bit RSA block authenticates the image.
Upon reset, the device mode pins are read to determine the primary boot device to be used: NAND,
Quad-SPI, SD, eMMC, or JTAG. JTAG can only be used as a non-secure boot source and is intended for
debugging purposes. The CSU executes code out of on-chip ROM and copies the first stage boot loader
(FSBL) from the boot device to the OCM.
After copying the FSBL to OCM, one of the processors, either the Cortex-A53 or Cortex-R5, executes the
FSBL. Xilinx supplies example FSBLs or users can create their own. The FSBL initiates the boot of the PS and
can load and configure the PL, or configuration of the PL can be deferred to a later stage. The FSBL
typically loads either a user application or an optional second stage boot loader (SSBL), such as U-Boot.
Users obtain example SSBL from Xilinx or a third party, or they can create their own SSBL. The SSBL
continues the boot process by loading code from any of the primary boot devices or from other sources
such as USB, Ethernet, etc. If the FSBL did not configure the PL, the SSBL can do so, or again, the
configuration can be deferred to a later stage.
The static memory interface controller (NAND, eMMC, or Quad-SPI) is configured using default settings.
To improve device configuration speed, these settings can be modified by information provided in the
boot image header. The ROM boot image is not user readable or callable after boot.
Hardware and Software Debug Support
The debug system used in Zynq UltraScale+ MPSoCs is based on the ARM CoreSight architecture. It uses
ARM CoreSight components including an embedded trace controller (ETC), an embedded trace Macrocell
(ETM) for each Cortex-A53 and Cortex-R5 processor, and a system trace Macrocell (STM). This enables
advanced debug features like event trace, debug breakpoints and triggers, cross-trigger, and debug bus
dump to memory. The programmable logic can be debugged with the Xilinx Vivado Logic Analyzer.
Debug Ports
Three JTAG ports are available and can be chained together or used separately. When chained together, a
single port is used for chip-level JTAG functions, ARM processor code downloads and run-time control
operations, PL configuration, and PL debug with the Vivado Logic Analyzer. This enables tools such as the
Xilinx Software Development Kit (SDK) and Vivado Logic Analyzer to share a single download cable from
Xilinx.
When the JTAG chain is split, one port is used to directly access the ARM DAP interface. This CoreSight
interface enables the use of ARM-compliant debug and software development tools such as Development
Studio 5 (DS-5™). The other JTAG port can then be used by the Xilinx FPGA tools for access to the PL,
including configuration bitstream downloads and PL debug with the Vivado Logic Analyzer. In this mode,
users can download to and debug the PL in the same manner as a stand-alone FPGA.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
39