DS891 Datasheet, PDF (5/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Table 2: Zynq UltraScale+ MPSoC: CG Device-Package Combinations and Maximum I/Os
Package
(1)(2)(3)(4)(5)
Package
Dimensions
(mm)
SBVA484⁽⁶⁾
19x19
SFVA625
21x21
SFVC784⁽⁷⁾
23x23
ZU2CG
HD, HP
GTH, GTY
24, 58
0, 0
24, 156
0, 0
96, 156
0, 0
FBVB900
31x31
FFVC900
31x31
FFVB1156
35x35
FFVC1156
35x35
FFVF1517
40x40
ZU3CG
HD, HP
GTH, GTY
24, 58
0, 0
24, 156
0, 0
96, 156
0, 0
ZU4CG
HD, HP
GTH, GTY
96, 156
4, 0
48, 156
16, 0
ZU5CG
HD, HP
GTH, GTY
96, 156
4, 0
48, 156
16, 0
ZU6CG
HD, HP
GTH, GTY
48, 156
16, 0
120, 208
24, 0
ZU7CG
HD, HP
GTH, GTY
48, 156
16, 0
48, 312
20, 0
48, 416
24, 0
ZU9CG
HD, HP
GTH, GTY
48, 156
16, 0
120, 208
24, 0
Notes:
1. Go to Ordering Information for package designation details.
2. FB/FF packages have 1.0mm ball pitch. SB/SF packages have 0.8mm ball pitch.
3. All device package combinations bond out 4 PS-GTR transceivers.
4. All device package combinations bond out 214 PS I/O except ZU2CG and ZU3CG in the SBVA484 and SFVA625 packages,
which bond out 170 PS I/Os.
5. Packages with the same last letter and number sequence, e.g., A484, are footprint compatible with all other UltraScale
devices with the same sequence. The footprint compatible devices within this family are outlined.
6. All 58 HP I/O pins are powered by the same V_CCO supply.
7. GTH transceivers in the SFVC784 package support data rates up to 12.5Gb/s.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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