DS891 Datasheet, PDF (36/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Digital Signal Processing
DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP
slices. All UltraScale architecture-based devices have many dedicated, low-power DSP slices, combining
high speed with small size while retaining system design flexibility.
Each DSP slice fundamentally consists of a dedicated 27 × 18 bit twos complement multiplier and a 48-bit
accumulator. The multiplier can be dynamically bypassed, and two 48-bit inputs can feed a
single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad
12-bit add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions
of the two operands.
The DSP includes an additional pre-adder, typically used in symmetrical filters. This pre-adder improves
performance in densely packed designs and reduces the DSP slice count by up to 50%. The 96-bit-wide
XOR function, programmable to 12, 24, 48, or 96-bit widths, enables performance improvements when
implementing forward error correction and cyclic redundancy checking algorithms.
The DSP also includes a 48-bit-wide pattern detector that can be used for convergent or symmetric
rounding. The pattern detector is also capable of implementing 96-bit-wide logic functions when used in
conjunction with the logic unit.
The DSP slice provides extensive pipelining and extension capabilities that enhance the speed and
efficiency of many applications beyond digital signal processing, such as wide dynamic bus shifters,
memory address generators, wide bus multiplexers, and memory-mapped I/O register files. The
accumulator can also be used as a synchronous up/down counter.
System Monitor
The System Monitor blocks in the UltraScale architecture are used to enhance the overall safety, security,
and reliability of the system by monitoring the physical environment via on-chip power supply and
temperature sensors.
All UltraScale architecture-based devices contain at least one System Monitor. The System Monitor in
UltraScale+ devices is similar to the Kintex UltraScale and Virtex UltraScale devices but with the addition
of a PMBus interface.
Zynq UltraScale+ MPSoCs contain one System Monitor in the PL and an additional block in the PS. The
System Monitor in the PL has the same features as the block in UltraScale+ FPGAs. See Table 11.
Table 11: Key System Monitor Features
Zynq UltraScale+ MPSoC PL
ADC
10-bit 200kSPS
Interfaces
JTAG, I2C, DRP, PMBus
Zynq UltraScale+ MPSoC PS
10-bit 1MSPS
APB
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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