DS891 Datasheet, PDF (21/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
• Sleep Mode with automatic wake-up
• Snoop Mode
• 16-bit timestamping for receive messages
• Both internal generated reference clock and external reference clock input from MIO
• Guarantee clock sampling edge between 80 to 83% at 24MHz reference clock input
• Optional eFUSE disable per port
USB 2.0
• Two USB controllers (configurable as USB 2.0 or USB 3.0)
• Host, device and On-The-Go (OTG) modes
• High Speed, Full Speed, and Low Speed
• Up to 12 endpoints
• 8-bit ULPI External PHY Interface
• The USB host controller registers and data structures are compliant to Intel xHCI specifications.
• 64-bit AXI master port with built-in DMA
• Power management features: hibernation mode
Static Memory Interfaces
The static memory interfaces support external static memories.
• ONFI 3.1 NAND flash support with up to 24-bit ECC
• 1-bit SPI, 2-bit SPI, 4-bit SPI (Quad-SPI), or two Quad-SPI (8-bit) serial NOR flash
• 8-bit eMMC interface supporting managed NAND flash
NAND ONFI 3.1 Flash Controller
• ONFI 3.1 compliant
• Supports chip select reduction per ONFI 3.1 spec
• SLC NAND for boot/configuration and data storage
• ECC options based on SLC NAND
o
1, 4, or 8 bits per 512+spare bytes
o
24 bits per 1024+spare bytes
• Maximum throughput as follows
o
Asynchronous mode (SDR) 24.3MB/s
o
Synchronous mode (NV-DDR) 112MB/s (for 100MHz flash clock)
• 8-bit SDR NAND interface
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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