DS891 Datasheet, PDF (13/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Real-Time Processing Unit (RPU)
• Dual-core ARM Cortex-R5 MPCores. Features associated with each core include:
o ARM v7-R Architecture (32-bit)
o Operating target frequency: Up to 600MHz
o A32/T32 instruction set support
o 4-way set-associative Level 1 caches (separate instruction and data, 32KB each) with ECC support
o Integrated Memory Protection Unit (MPU) per processor
o 128KB Tightly Coupled Memory (TCM) with ECC support
o TCMs can be combined to become 256KB in lockstep mode
• Ability to operate in single-processor or dual-processor modes (split and lock-step)
• Little and big endian support
• Dedicated SWDT and two Triple Timer Counters (TTC)
• CoreSight debug and trace support
o Embedded Trace Macrocell (ETM) for instruction and trace
o Cross trigger interface (CTI) enabling hardware breakpoints and triggers
• Optional eFUSE disable
Full-Power Domain DMA (FPD-DMA) and Low-Power Domain DMA
(LPD-DMA)
• Two general-purpose DMA controllers one in the full-power domain (FPD-DMA) and one in the low-power
domain (LPD-DMA)
• Eight independent channels per DMA
• Multiple transfer types:
o Memory-to-memory
o Memory-to-peripheral
o Peripheral-to-memory and
o Scatter-gather
• 8 peripheral interfaces per DMA
• TrustZone per DMA for optional secure operation
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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