DS891 Datasheet, PDF (8/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Table 5: Zynq UltraScale+ MPSoC: EV Device Feature Summary
Application Processing Unit
Real-Time Processing Unit
Embedded and External
Memory
General Connectivity
High-Speed Connectivity
Graphic Processing Unit
Video Codec
System Logic Cells
CLB Flip-Flops
CLB LUTs
Distributed RAM (Mb)
Block RAM Blocks
Block RAM (Mb)
UltraRAM Blocks
UltraRAM (Mb)
DSP Slices
CMTs
Max. HP I/O⁽¹⁾
Max. HD I/O⁽²⁾
System Monitor
GTH Transceiver 16.3Gb/s⁽³⁾
GTY Transceivers 32.75Gb/s
Transceiver Fractional PLLs
PCIe Gen3 x16 and Gen4 x8
150G Interlaken
100G Ethernet w/ RS-FEC
ZU4EV
ZU5EV
ZU7EV
Quad-core ARM Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision Floating Point;
32KB/32KB L1 Cache, 1MB L2 Cache
Dual-core ARM Cortex-R5 with CoreSight; Single/Double Precision Floating Point; 32KB/32KB L1
Cache, and TCM
256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3;
External Quad-SPI; NAND; eMMC
214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; WatchDog Timers; Triple
Timer Counters
4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII
ARM Mali™-400 MP2; 64KB L2 Cache
1
1
1
192,150
256,200
504,000
175,680
234,240
460,800
87,840
117,120
230,400
2.6
3.5
6.2
128
144
312
4.5
5.1
11.0
48
64
96
14.0
18.0
27.0
728
1,056
1,728
4
4
8
156
156
416
96
96
48
2
2
2
16
16
24
0
0
0
8
8
12
2
2
2
0
0
0
0
0
0
Notes:
1. HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V.
2. HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V.
3. GTH transceivers in the SFVC784 package support data rates up to 12.5Gb/s. See Table 6.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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