DS891 Datasheet, PDF (19/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
• Full duplex flow control with recognition of incoming pause frames and hardware generation of
transmitted pause frames
• 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames
• Supports IEEE Std 1588 v2
SD/SDIO 3.0 Controller
In addition to secure digital (SD) devices, this controller also supports eMMC 4.51.
• Host mode support only
• Built-in DMA
• 1/4-Bit SD Specification, version 3.0
• 1/4/8-Bit eMMC Specification, version 4.51
• Supports primary boot from SD Card and eMMC (Managed NAND)
• High speed, default speed, and low-speed support
• 1 and 4-bit data interface support
o Low speed clock 0-400KHz
o Default speed 0-25MHz
o High speed clock 0-50MHz
• High speed Interface
o SD UHS-1: 208MHz
o eMMC HS200: 200MHz
• Memory, I/O, and SD cards
• Power control modes
• Data FIFO interface up to 512B
UART
• Programmable baud rate generator
• 6, 7, or 8 data bits
• 1, 1.5, or 2 stop bits
• Odd, even, space, mark, or no parity
• Parity, framing, and overrun error detection
• Line break generation and detection
• Automatic echo, local loopback, and remote loopback channel modes
• Modem control signals: CTS, RTS, DSR, DTR, RI, and DCD (from EMIO only)
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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