DS891 Datasheet, PDF (15/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
• Low power modes
o Active/precharge power down
o Self-refresh, including clean exit from self-refresh after a controller power cycle
• Enhanced DDR training by allowing software to measure read/write eye and make delay adjustments
dynamically
• Independent performance monitors for read path and write path
• Integration of PHY Debug Access Port (DAP) into JTAG for testing
The DDR memory controller is multi-ported and enables the PS and the PL to have shared access to a
common memory. The DDR controller features six AXI slave ports for this purpose:
• Two 128-bit AXI ports from the ARM Cortex-A53 CPU(s), RPU (ARM Cortex-R5 and LPD peripherals), GPU,
high speed peripherals (USB3, PCIe & SATA), and High Performance Ports (HP0 & HP1) from the PL
through the Cache Coherent Interconnect (CCI)
• One 64-bit port is dedicated for the ARM Cortex-R5 CPU(s)
• One 128-bit AXI port from the DisplayPort and HP2 port from the PL
• One 128-bit AXI port from HP3 and HP4 ports from the PL
• One 128-bit AXI port from General DMA and HP5 from the PL
High-Speed Connectivity Peripherals
PCIe
• Compliant with the PCI Express Base Specification 2.1
• Fully compliant with PCI Express transaction ordering rules
• Lane width: x1, x2, or x4 at Gen1 or Gen2 rates
• 1 Virtual Channel
• Full duplex PCIe port
• End Point and single PCIe link Root Port
• Root Port supports Enhanced Configuration Access Mechanism (ECAM), Cfg Transaction generation
• Root Port support for INTx, and MSI
• Endpoint support for MSI or MSI-X
o 1 physical function, no SR-IOV
o No relaxed or ID ordering
o Fully configurable BARs
o INTx not recommended, but can be generated
o Endpoint to support configurable target/slave apertures with address translation and Interrupt
capability
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
15