DS891 Datasheet, PDF (35/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Programmable Data Width
Each port can be configured as 32K × 1; 16K × 2; 8K × 4; 4K × 9 (or 8); 2K × 18 (or 16); 1K × 36 (or 32); or
512 × 72 (or 64). Whether configured as block RAM or FIFO, the two ports can have different aspect ratios
without any constraints. Each block RAM can be divided into two completely independent 18Kb block
RAMs that can each be configured to any aspect ratio from 16K × 1 to 512 × 36. Everything described
previously for the full 36Kb block RAM also applies to each of the smaller 18Kb block RAMs. Only in simple
dual-port (SDP) mode can data widths of greater than 18 bits (18Kb RAM) or 36 bits (36Kb RAM) be
accessed. In this mode, one port is dedicated to read operation, the other to write operation. In SDP mode,
one side (read or write) can be variable, while the other is fixed to 32/36 or 64/72. Both sides of the
dual-port 36Kb RAM can be of variable width.
Error Detection and Correction
Each 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and
perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC
logic can also be used when writing to or reading from external 64- to 72-bit-wide memories.
FIFO Controller
Each block RAM can be configured as a 36Kb FIFO or an 18Kb FIFO. The built-in FIFO controller for
single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments the internal
addresses and provides four handshaking flags: full, empty, programmable full, and programmable empty.
The programmable flags allow the user to specify the FIFO counter values that make these flags go active.
The FIFO width and depth are programmable with support for different read port and write port widths on
a single FIFO. A dedicated cascade path allows for easy creation of deeper FIFOs.
UltraRAM
UltraRAM is a high-density, dual-port, synchronous memory block used in some UltraScale+ families. Both
of the ports share the same clock and can address all of the 4K x 72 bits. Each port can independently read
from or write to the memory array. UltraRAM supports two types of write enable schemes. The first mode
is consistent with the block RAM byte write enable mode. The second mode allows gating the data and
parity byte writes separately. Multiple UltraRAM blocks can be cascaded together to create larger memory
arrays. UltraRAM blocks can be connected together to create larger memory arrays. Dedicated routing in
the UltraRAM column enables the entire column height to be connected together. This makes UltraRAM an
ideal solution for replacing external memories such as SRAM. Cascadable anywhere from 288Kb to 36Mb,
UltraRAM provides the flexibility to fulfill many different memory requirements.
Error Detection and Correction
Each 64-bit-wide UltraRAM can generate, store and utilize eight additional Hamming code bits and
perform single-bit error correction and double-bit error detection (ECC) during the read process.
DS891 (v1.3) September 23, 2016
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Advance Product Specification
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