DS891 Datasheet, PDF (22/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

• 2 chip selects
• Programmable access timing
• 1.8V and 3.3V I/O
• Built-in DMA for improved performance
Quad-SPI Controller
• 4 bytes (32-bit) and 3 bytes (24-bit) address width
• Maximum SPI Clock at Master Mode at 150MHz
• Single, Dual-Parallel, and Dual-Stacked mode
• 32-bit AXI Linear Address Mapping Interface for read operation
• Up to 2 chip select signals
• Write Protection Signal
• Hold signals
• 4-bit bidirectional I/O signals
• x1/x2/x4 Read speed required
• x1 write speed required only
• 64 byte Entry FIFO depth to improve QSPI read efficiency
• Built-in DMA for improved performance
Zynq UltraScale+ MPSoC Overview
Video Encoder/Decoder (VCU)
Zynq UltraScale+ MPSoCs include a Video codec (encoder/decoder) available in the devices designated
with the EV suffix. The VCU is located in the PL and can be accessed from either the PL or PS.
• Simultaneous Encode and Decode through separate cores
• H.264 high profile level 5.2 (4Kx2K-60)
• H.265 (HEVC) main, main10 profile, level 5.1, high Tier, up to 4Kx2K-60 rate
• 8 and 10 bit encoding
• 4:2:0 and 4:2:2 chroma sampling
• 8Kx4K-15 rate
• Multi-stream up to total of 4Kx2K-60 rate
• Low Latency mode
• Can share the PS DRAM or use dedicated DRAM in the PL
• Clock/power management
• OpenMax Linux drivers
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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