DS891 Datasheet, PDF (3/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Programmable Logic (PL)
Configurable Logic Blocks (CLB)
• Look-up tables (LUT)
• Flip-flops
• Cascadable adders
36Kb Block RAM
• True dual-port
• Up to 72 bits wide
• Configurable as dual 18Kb
UltraRAM
• 288Kb dual-port
• 72 bits wide
• Error checking and correction
DSP Blocks
• 27 x 18 signed multiply
• 48-bit adder/accumulator
• 27-bit pre-adder
Programmable I/O Blocks
• Supports LVCMOS, LVDS, and SSTL
• 1.0V to 3.3V I/O
• Programmable I/O delay and SerDes
JTAG Boundary-Scan
• IEEE Std 1149.1 Compatible Test Interface
Zynq UltraScale+ MPSoC Overview
PCI Express
• Supports Root complex and End Point
configurations
• Supports up to Gen4 speeds
• Up to five integrated blocks in select devices
100G Ethernet MAC/PCS
• IEEE Std 802.3 compliant
• CAUI-10 (10x 10.3125Gb/s) or
CAUI-4 (4x 25.78125Gb/s)
• RSFEC (IEEE Std 802.3bj) in CAUI-4 configuration
• Up to four integrated blocks in select devices
Interlaken
• Interlaken spec 1.2 compliant
• 64/67 encoding
• 12 x 12.5Gb/s or 6 x 25Gb/s
• Up to four integrated blocks in select devices
Video Encoder/Decoder (VCU)
• Available in EV devices
• Accessible from either PS or PL
• Simultaneous encode and decode
• H.264 and H.265 support
System Monitor in PL
• On-chip voltage and temperature sensing
• 10-bit 200KSPS ADC with up to 17 external inputs
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
3