DS891 Datasheet, PDF (24/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Table 8: MIO Peripheral Interface Mapping
Peripheral
Interface
MIO
EMIO
Quad-SPI
Yes
No
NAND
USB2.0: 0,1
Yes: External PHY
No
SDIO 0,1
Yes
Yes
SPI: 0,1
I2C: 0,1
CAN: 0,1
GPIO
Yes
CAN: External PHY
GPIO: Up to 78 bits
Yes
CAN: External PHY
GPIO: Up to 96 bits
GigE: 0,1,2,3
RGMII v2.0:
External PHY
Supports GMII, RGMII v2.0 (HSTL), RGMII v1.3, MII, SGMII, and
1000BASE-X in Programmable Logic
UART: 0,1
Simple UART:
Only two pins (TX and RX)
Debug Trace Ports Yes: Up to 16 trace bits
Full UART (TX, RX, DTR, DCD, DSR, RI, RTS, and CTS) requires either:
• Two Processing System (PS) pins (RX and TX) through MIO and six
additional Programmable Logic (PL) pins, or
• Eight Programmable Logic (PL) pins
Yes: Up to 32 trace bits
Processor JTAG Yes
Yes
Transceiver (PS-GTR)
The four PS-GTR transceivers, which reside in the full power domain (FPD), support data rates of up to
6.0Gb/s. All the protocols cannot be pinned out at the same time. At any given time, four differential pairs
can be pinned out using the transceivers. This is user programmable via the high-speed I/O multiplexer
(HS-MIO).
• A Quad transceiver PS-GTR (TX/RX pair) able to support following standards simultaneously
o x1, x2, or x4 lane of PCIe at Gen1 (2.5Gb/s) or Gen2 (5.0Gb/s) rates
o 1 or 2 lanes of DisplayPort (TX only) at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s
o 1 or 2 SATA channels at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s
o 1 or 2 USB3.0 channels at 5.0Gb/s
o 1-4 Ethernet SGMII channels at 1.25Gb/s
• Provides flexible host-programmable multiplexing function for connecting the transceiver resources to the
PS masters (DisplayPort, PCIe, Serial-ATA, USB3.0, and GigE).
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
24