DS891 Datasheet, PDF (26/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
High-Performance AXI Ports
The high-performance AXI4 ports provide access from the PL to DDR and high-speed interconnect in the
PS. The six dedicated AXI memory ports from the PL to the PS are configurable as either 128-bit, 64-bit,
or 32-bit interfaces. These interfaces connect the PL to the memory interconnect via a FIFO interface. Two
of the AXI interfaces support I/O coherent access to the APU caches.
Each high-performance AXI port has these characteristics:
• Reduced latency between PL and processing system memory
• 1KB deep FIFO
• Configurable either as 128-bit, 64-bit, or 32-bit AXI interfaces
• Multiple AXI command issuing to DDR
Accelerator Coherency Port (ACP)
The Zynq UltraScale+ MPSoC accelerator coherency port (ACP) is a 64-bit AXI slave interface that provides
connectivity between the APU and a potential accelerator function in the PL. The ACP directly connects the
PL to the snoop control unit (SCU) of the ARM Cortex-A53 processors, enabling cache-coherent access to
CPU data in the L2 cache. The ACP provides a low latency path between the PS and a PL-based accelerator
when compared with a legacy cache flushing and loading scheme. The ACP only snoops access in the CPU
L2 cache, providing coherency in hardware. It does not support coherency on the PL side. So this interface
is ideal for a DMA or an accelerator in the PL that only requires coherency on the CPU cache memories. For
example, if a MicroBlaze™ processor in the PL is attached to the ACP interface, the cache of MicroBlaze
processor will not be coherent with Cortex-A53 caches.
AXI Coherency Extension (ACE)
The Zynq UltraScale+ MPSoC AXI coherency extension (ACE) is a 64-bit AXI4 slave interface that provides
connectivity between the APU and a potential accelerator function in the PL. The ACE directly connects the
PL to the snoop control unit (SCU) of the ARM Cortex-A53 processors, enabling cache-coherent access to
Cache Coherent Interconnect (CCI). The ACE provides a low-latency path between the PS and a PL-based
accelerator when compared with a legacy cache flushing and loading scheme. The ACE snoops accesses to
the CCI and the PL side, thus, providing full coherency in hardware. This interface can be used to hook up
a cached interface in the PL to the PS as caches on both the Cortex-A53 memories and the PL master are
snooped thus providing full coherency. For example, if a MicroBlaze processor in the PL is hooked up using
an ACE interface, then Cortex-A53 and MicroBlaze processor caches will be coherent with each other.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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