DS891 Datasheet, PDF (32/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Integrated Block for 100G Ethernet
Compliant to the IEEE Std 802.3ba, the 100G Ethernet integrated blocks in the UltraScale architecture
provide low latency 100Gb/s Ethernet ports with a wide range of user customization and statistics
gathering. With support for 10 x 10.3125Gb/s (CAUI) and 4 x 25.78125Gb/s (CAUI-4) configurations, the
integrated block includes both the 100G MAC and PCS logic with support for IEEE Std 1588v2 1-step and
2-step hardware timestamping.
In UltraScale+ devices, the 100G Ethernet blocks contain a Reed Solomon Forward Error Correction
(RS-FEC) block, compliant to IEEE Std 802.3bj, that can be used with the Ethernet block or stand alone in
user applications. These families also support OTN mapping mode in which the PCS can be operate
without using the MAC.
Clock Management
The clock generation and distribution components in UltraScale architecture-based devices are located
adjacent to the columns that contain the memory interfacing and input and output circuitry. This tight
coupling of clocking and I/O provides low-latency clocking to the I/O for memory interfaces and other I/O
protocols. Within every clock management tile (CMT) resides one mixed-mode clock manager (MMCM),
two PLLs, clock distribution buffers and routing, and dedicated circuitry for implementing external
memory interfaces.
Mixed-Mode Clock Manager
The mixed-mode clock manager (MMCM) can serve as a frequency synthesizer for a wide range of
frequencies and as a jitter filter for incoming clocks. At the center of the MMCM is a voltage-controlled
oscillator (VCO), which speeds up and slows down depending on the input voltage it receives from the
phase frequency detector (PFD).
Three sets of programmable frequency dividers (D, M, and O) are programmable by configuration and
during normal operation via the Dynamic Reconfiguration Port (DRP). The pre-divider D reduces the input
frequency and feeds one input of the phase/frequency comparator. The feedback divider M acts as a
multiplier because it divides the VCO output frequency before feeding the other input of the phase
comparator. D and M must be chosen appropriately to keep the VCO within its specified frequency range.
The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each
phase can be selected to drive one of the output dividers, and each divider is programmable by
configuration to divide by any integer from 1 to 128.
The MMCM has three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode.
Low-Bandwidth mode has the best jitter attenuation. High-Bandwidth mode has the best phase offset.
Optimized mode allows the tools to find the best setting.
The MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one
output path. Fractional counters allow non-integer increments of 1/8 and can thus increase frequency
synthesis capabilities by a factor of 8. The MMCM can also provide fixed or dynamic phase shift in small
increments that depend on the VCO frequency. At 1,600MHz, the phase-shift timing increment is 11.2ps.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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