DS891 Datasheet, PDF (33/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
PLL
With fewer features than the MMCM, the two PLLs in a clock management tile are primarily present to
provide the necessary clocks to the dedicated memory interface circuitry. The circuit at the center of the
PLLs is similar to the MMCM, with PFD feeding a VCO and programmable M, D, and O counters. There are
two divided outputs to the device fabric per PLL as well as one clock plus one enable signal to the memory
interface circuitry.
Zynq UltraScale+ MPSoCs are equipped with five additional PLLs in the PS for independently configuring
the four primary clock domains with the PS: the APU, the RPU, the DDR controller, and the I/O peripherals.
Clock Distribution
Clocks are distributed throughout Zynq UltraScale+ MPSoCs via buffers that drive a number of vertical
and horizontal tracks. There are 24 horizontal clock routes per clock region and 24 vertical clock routes per
clock region with 24 additional vertical clock routes adjacent to the MMCM and PLL. Within a clock region,
clock signals are routed to the device logic (CLBs, etc.) via 16 gateable leaf clocks.
Several types of clock buffers are available. The BUFGCE and BUFCE_LEAF buffers provide clock gating at
the global and leaf levels, respectively. BUFGCTRL provides glitchless clock muxing and gating capability.
BUFGCE_DIV has clock gating capability and can divide a clock by 1 to 8. BUFG_GT performs clock division
from 1 to 8 for the transceiver clocks. In MPSoCs, clocks can be transferred from the PS to the PL using
dedicated buffers.
Memory Interfaces
Memory interface data rates continue to increase, driving the need for dedicated circuitry that enables
high performance, reliable interfacing to current and next-generation memory technologies. Every
Zynq UltraScale+ MPSoC includes dedicated physical interfaces (PHY) blocks located between the CMT
and I/O columns that support implementation of high-performance PHY blocks to external memories such
as DDR4, DDR3, QDRII+, and RLDRAM3. The PHY blocks in each I/O bank generate the address/control
and data bus signaling protocols as well as the precision clock/data alignment required to reliably
communicate with a variety of high-performance memory standards. Multiple I/O banks can be used to
create wider memory interfaces.
As well as external parallel memory interfaces, Zynq UltraScale+ MPSoC can communicate to external
serial memories, such as Hybrid Memory Cube (HMC), via the high-speed serial transceivers. All
transceivers in the UltraScale architecture support the HMC protocol, up to 15Gb/s line rates. UltraScale
architecture-based devices support the highest bandwidth HMC configuration of 64 lanes with a single
device.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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