DS891 Datasheet, PDF (38/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Clock Management
The PS in Zynq UltraScale+ MPSoCs is equipped with five phase-locked loops (PLLs), providing flexibility
in configuring the clock domains within the PS. There are four primary clock domains of interest within the
PS. These include the APU, the RPU, the DDR controller, and the I/O peripherals (IOP). The frequencies of
all of these domains can be configured independently under software control.
Power Domains
The Zynq UltraScale+ MPSoC contains four separate power domains. When they are connected to
separate power supplies, they can be completely powered down independently of each other without
consuming any dynamic or static power. The processing system includes:
• Full Power Domain (FPD)
• Low Power Domain (LPD)
• Battery Powered Domain (BPD)
In addition to these three Processing System power domains, the PL can also be completely powered
down if connected to separate power supplies.
The Full Power Domain (FPD) consists of the following major blocks:
• Application Processing Unit (APU)
• DMA (FP-DMA)
• Graphics Processing Unit (GPU)
• Dynamic Memory Controller (DDRC)
• High-Speed I/O Peripherals
The Low Power Domain (LPD) consists of the following major blocks:
• Real-Time Processing Unit (RPU)
• DMA (LP-DMA)
• Platform Management Unit (PMU)
• Configuration Security Unit (CSU)
• Low-Speed I/O Peripherals
• Static Memory Interfaces
The Battery Power Domain (BPD) is the lowest power domain of the Zynq UltraScale+ MPSoC processing
system. In this mode, all the PS is powered off except the Real-Time Clock (RTC) and battery-backed RAM
(BBRAM).
Power Examples
Power for the Zynq UltraScale+ MPSoCs varies depending on the utilization of the PL resources, and the
frequency of the PS and PL. To estimate power, use the Xilinx Power Estimator (XPE) at:
http://www.xilinx.com/products/design_tools/logic_design/xpe.htm
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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