DS891 Datasheet, PDF (20/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
SPI
• Full-duplex operation offers simultaneous receive and transmit
• 128B deep read and write FIFO
• Master or slave SPI mode
• Up to 3 chip select lines
• Multi-master environment
• Identifies an error condition if more than one master detected
• Selectable master clock reference
• Software can poll for status or be interrupt driven
I2C
• 128-bit buffer size
• Both normal (100kHz) and fast bus data rates (400kHz)
• Master or slave mode
• Normal or extended addressing
• I2C bus hold for slow host service
GPIO
• Up to 128 GPIO bits
o Up to 78-bits from MIO and 96-bits from EMIO
• Each GPIO bit can be dynamically programmed as input or output
• Independent reset values for each bit of all registers
• Interrupt request generation for each GPIO signals
• Single Channel (Bit) write capability for all control registers include data output register, direction control
register, and interrupt clear register
• Read back in output mode
CAN
• Conforms to the ISO 11898 -1, CAN2.0A, and CAN 2.0B standards
• Both standard (11-bit identifier) and extended (29-bit identifier) frames
• Bit rates up to 1Mb/s
• Transmit and Receive message FIFO with a depth of 64 messages
• Watermark interrupts for TXFIFO and RXFIFO
• Automatic re-transmission on errors or arbitration loss in normal mode
• Acceptance filtering of 4 acceptance filters
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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