DS891 Datasheet, PDF (2/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
ARM Mali-400 Based GPU
• Supports OpenGL ES 1.1 and 2.0
• Supports OpenVG 1.1
• GPU frequency: Up to 667MHz
• Single Geometry Processor, Two Pixel Processors
• Pixel Fill Rate: 2 Mpixels/sec/MHz
• Triangle Rate: 0.11 Mtriangles/sec/MHz
• 64KB L2 Cache
• Power island gating
External Memory Interfaces
• Multi-protocol dynamic memory controller
• 32-bit or 64-bit interfaces to DDR4, DDR3,
DDR3L, or LPDDR3 memories, and 32-bit
interface to LPDDR4 memory
• ECC support in 64-bit and 32-bit modes
• Up to 32GB of address space using single or dual
rank of 8-, 16-, or 32-bit-wide memories
• Static memory interfaces
o eMMC4.51 Managed NAND flash support
o ONFI3.1 NAND flash with 24-bit ECC
o 1-bit SPI, 2-bit SPI, 4-bit SPI (Quad-SPI), or
two Quad-SPI (8-bit) serial NOR flash
8-Channel DMA Controller
• Two DMA controllers of 8-channels each
• Memory-to-memory, memory-to-peripheral,
peripheral-to-memory, and scatter-gather
transaction support
Serial Transceivers
• Four dedicated PS-GTR receivers and
transmitters supports up to 6.0Gb/s data rates
o Supports SGMII tri-speed Ethernet, PCI
Express® Gen2, Serial-ATA (SATA), USB3.0,
and DisplayPort
Dedicated I/O Peripherals and
Interfaces
• PCI Express — Compliant with PCIe® 2.1 base
specification
o Root complex and End Point configurations
o x1, x2, and x4 at Gen1 or Gen2 rates
• SATA Host
o 1.5, 3.0, and 6.0Gb/s data rates as defined by
SATA Specification, revision 3.1
o Supports up to two channels
• DisplayPort Controller
o Up to 5.4Gb/s rate
o Up to two TX lanes (no RX support)
• Four 10/100/1000 tri-speed Ethernet MAC
peripherals with IEEE Std 802.3 and IEEE Std 1588
revision 2.0 support
o Scatter-gather DMA capability
o Recognition of IEEE Std 1588 rev.2 PTP frames
o GMII, RGMII, and SGMII interfaces
o Jumbo frames
• Two USB 3.0/2.0 Device, Host, or OTG peripherals,
each supporting up to 12 endpoints
o USB 3.0/2.0 compliant device IP core
o Super-speed, high- speed, full-speed, and
low-speed modes
o Intel XHCI- compliant USB host
• Two full CAN 2.0B-compliant CAN bus interfaces
o CAN 2.0-A and CAN 2.0-B and ISO 118981-1
standard compliant
• Two SD/SDIO 2.0/eMMC4.51 compliant
controllers
• Two full-duplex SPI ports with three peripheral
chip selects
• Two high-speed UARTs (up to 1Mb/s)
• Two master and slave I2C interfaces
• Up to 78 flexible multiplexed I/O (MIO) (up to
three banks of 26 I/Os) for peripheral pin
assignment
• Up to 96 EMIOs (up to three banks of 32 I/Os)
connected to the PL
Interconnect
• High-bandwidth connectivity within PS
and between PS and PL
• ARM AMBA® AXI4-based
• QoS support for latency and bandwidth control
• Cache Coherent Interconnect (CCI)
System Memory Management
• System Memory Management Unit (SMMU)
• Xilinx Memory Protection Unit (XMPU)
Platform Management Unit
• Power gates PS peripherals, power islands, and
power domains
• Clock gates PS peripheral user firmware option
Configuration and Security Unit
• Boots PS and configures PL
• Supports secure and non-secure boot modes
System Monitor in PS
• On-chip voltage and temperature sensing
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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