DS891 Datasheet, PDF (28/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

X-Ref Target - Figure 2
Clock Region Width
Clock
Region
Height
Zynq UltraScale+ MPSoC Overview
For graphical representation only, does not represent a real device.
DS891_02_012915
Figure 2: Column-Based Device Divided into Clock Regions
Input/Output
All Zynq UltraScale+ MPSoCs have I/O pins for communicating to external components. In addition, in the
MPSoC’s PS, there are another 78 I/Os that the I/O peripherals use to communicate to external
components, referred to as multiplexed I/O (MIO). If more than 78 pins are required by the I/O peripherals,
the I/O pins in the PL can be used to extend the MPSoC interfacing capability, referred to as extended MIO
(EMIO).
The number of I/O pins in the PL of Zynq UltraScale+ MPSoCs varies depending on device and package.
Each I/O is configurable and can comply with a large number of I/O standards. The I/Os are classed as
high-performance (HP), or high-density (HD). The HP I/Os are optimized for highest performance
operation, from 1.0V to 1.8V. The HD I/Os are reduced-feature I/Os organized in banks of 24, providing
voltage support from 1.2V to 3.3V.
All I/O pins are organized in banks, with 52 HP pins per bank or 24 HD pins per bank. Each bank has one
common V_CCO output buffer power supply, which also powers certain input buffers. Some single-ended
input buffers require an internally generated or an externally applied reference voltage (V_REF). V_REF pins
can be driven directly from the PCB or internally generated using the internal V_REF generator circuitry
present in each bank.
I/O Electrical Characteristics
Single-ended outputs use a conventional CMOS push/pull output structure driving High towards V_CCO or
Low towards ground, and can be put into a high-Z state. The system designer can specify the slew rate and
the output strength. The input is always active but is usually ignored while the output is active. Each pin
can optionally have a weak pull-up or a weak pull-down resistor.
Most signal pin pairs can be configured as differential input pairs or output pairs. Differential input pin
pairs can optionally be terminated with a 100Ω internal resistor. All UltraScale architecture-based devices
support differential standards beyond LVDS, including RSDS, BLVDS, differential SSTL, and differential
HSTL. Each of the I/Os supports memory I/O standards, such as single-ended and differential HSTL as well
as single-ended and differential SSTL.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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