DS891 Datasheet, PDF (27/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Programmable Logic
This section covers the information about blocks in the Programmable Logic (PL).
Device Layout
UltraScale architecture-based devices are arranged in a column-and-grid layout. Columns of resources are
combined in different ratios to provide the optimum capability for the device density, target market or
application, and device cost. At the core of UltraScale+ MPSoCs is the processing system that displaces
some of the full or partial columns of programmable logic resources. Figure 1 shows a device-level view
with resources grouped together. For simplicity, certain resources such as the processing system,
integrated blocks for PCIe, configuration logic, and System Monitor are not shown.
X-Ref Target - Figure 1
DS891_01_012915
Figure 1: Device with Columnar Resources
Resources within the device are divided into segmented clock regions. The height of a clock region is
60 CLBs. A bank of 52 I/Os, 24 DSP slices, 12 block RAMs, or 4 transceiver channels also matches the height
of a clock region. The width of a clock region is essentially the same in all cases, regardless of device size
or the mix of resources in the region, enabling repeatable timing results. Each segmented clock region
contains vertical and horizontal clock routing that span its full height and width. These horizontal and
vertical clock routes can be segmented at the clock region boundary to provide a flexible,
high-performance, low-power clock distribution architecture. Figure 2 is a representation of a device
divided into regions.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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