DS891 Datasheet, PDF (25/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
HS-MIO
The function of the HS-MIO is to multiplex access from the high-speed PS peripheral to the differential
pair on the PS-GTR transceiver as defined in the configuration registers. Up to 4 channels of the
transceiver are available for use by the high-speed interfaces in the PS.
Table 9: HS-MIO Peripheral Interface Mapping
Peripheral Interface
Lane0
PCIe (x1, x2 or x4)
PCIe0
SATA (1 or 2 channels)
SATA0
DisplayPort (TX only)
DP1
USB0
USB0
USB1
–
SGMII0
SGMII0
SGMII1
–
SGMII2
–
SGMII3
–
Lane1
PCIe1
SATA1
DP0
USB0
–
–
SGMII1
–
–
Lane2
PCIe2
SATA0
DP1
USB0
–
–
–
SGMII2
–
Lane3
PCIe3
SATA1
DP0
–
USB1
–
–
–
SGMII3
PS-PL Interface
The PS-PL interface includes:
• AMBA AXI4 interfaces for primary data communication
o Six 128-bit/64-bit/32-bit High Performance (HP) Slave AXI interfaces from PL to PS.
– Four 128-bit/64-bit/32-bit HP AXI interfaces from PL to PS DDR.
– Two 128-bit/64-bit/32-bit high-performance coherent (HPC) ports from PL to cache coherent
interconnect (CCI).
o Two 128-bit/64-bit/32-bit HP Master AXI interfaces from PS to PL.
o One 128-bit/64-bit/32-bit interface from PL to RPU in PS (PL_LPD) for low latency access to OCM.
o One 128-bit/64-bit/32-bit AXI interface from RPU in PS to PL (LPD_PL) for low latency access to PL.
o One 128-bit AXI interface (ACP port) for I/O coherent access from PL to Cortex-A53 cache memory.
This interface provides coherency in hardware for Cortex-A53 cache memory.
o One 128-bit AXI interface (ACE Port) for Fully coherent access from PL to Cortex-A53. This interface
provides coherency in hardware for Cortex-A53 cache memory and the PL.
• Clocks and resets
o Four PS clock outputs to the PL with start/stop control.
o Four PS reset outputs to the PL.
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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